I am a Verilog user trying to make sense of VHDL code of AXI4 master bus functional model (BFM).

AXI bus master VHDL code

I have a few questions from the above code:

What would the block diagram of the code look like (how are components connected with each other)?

Lastly, what is the use of the FIFO? I mean to connect AXI master to AXI slave, can't one connect the appropriate signals directly as shown in the picture? What purpose does the FIFO serve here and what if it is removed?

enter image description here

  • 1
    \$\begingroup\$ duplicate of AXI master bus functional model in vhdl \$\endgroup\$
    – JHBonarius
    Commented Apr 6, 2017 at 7:18
  • 2
    \$\begingroup\$ AFAIU, the the contents of the AXI burst reads and writes are stored in FIFOs, to be accessed with the signals "address/write_data/read_data/write_fifo_en/..." etc. Yes, you can connect an AXI master to an AXI slave with nothing but wires. \$\endgroup\$
    – Grabul
    Commented May 7, 2017 at 18:00

2 Answers 2


As I understand, there in your code describes connection of two FIFOs. Its exactly connected as on the picture, but in your case components are FIFOs. Here could be many reasons to use these FIFOs, but if you remove it, data exchange will be corrupted.
To clarify what exactly purpose of FIFOs you need to look where this module connected.


In an AXI4 Manager (either RTL or a Verification component), you need a FIFO between the operation dispatch side (aka the user or transaction interface) that wants to do a read or write operation on the AXI4 interface and the 5 independent channels of the AXI4 interface (address write, write data, write response, address read, and read data) in order to be able to independently exercise each channel of the AXI interface independently.


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