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I am a Verilog user trying to make sense of VHDL code of AXI4 Master bus functional model (BFM)

AXI bus master VHDL code

I have a few questions from the above code

What would block diagram of the code look like (how are components connected with each other)

Lastly, what is the use of FIFO? I mean to connect AXI master to AXI slave, can't one connect the appropriate signals directly as shown in the picture? What purpose does FIFO serve here and what if it is removed?

enter image description here

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  • \$\begingroup\$ duplicate of AXI master bus functional model in vhdl \$\endgroup\$ – JHBonarius Apr 6 '17 at 7:18
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    \$\begingroup\$ AFAIU, the the contents of the AXI burst reads and writes are stored in FIFOs, to be accessed with the signals "address/write_data/read_data/write_fifo_en/..." etc. Yes, you can connect an AXI master to an AXI slave with nothing but wires. \$\endgroup\$ – TEMLIB May 7 '17 at 18:00
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As I understand, there in your code describes connection of two FIFOs. Its exactly connected as on the picture, but in your case components are FIFOs. Here could be many reasons to use these FIFOs, but if you remove it, data exchange will be corrupted.
To clarify what exactly purpose of FIFOs you need to look where this module connected.

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