What is the current return path in this condition

Question

When there is a reference plane the return current will be on it and if that plane is continuous then it is perfect.

However i studied board designs like arduino due etc. They dont have any dedicated ground or vcc plane. It is just 2 layer pcb so they just draw traces for every connection. So in this condition the routing is a mess and what is the return currents path? I mean if you say it will follow the lowest impedance. What is it where is it. For example can the lowest impedance road be another signals trace. If so how they manage to make this board work there is tens of traces to worry.

Answer 1

I suspect that the board in your picture is a four layer board, with only the surface layers shown. There are a number of GND pins which have no apparent connection, so they very probably connect to a ground plane on an inner layer.

However, for simpler circuits it is entirely possible to design a PC Board without any ground or power planes - you use regular surface tracks (but probably wider than signal tracks) for the power and ground connections.

Answer 2

Any current in electrical conductors generates a magnetic field; such current is caused by voltage differences (i.e. an electric field). So, one can solve for the current in a messy ground interconnection by knowing the nodes that source and sink current, and setting up the interconnected equations of field effects (such as inductance, resistance, capacitance) in the metal parts.

The picture shows only two layers of wiring, but a third (ground plane) layer is implied by the labels.

A ground plane, and power planes, are intended to make such a detailed calculation unnecessary. Inductance and resistance are both low when you use big pieces of copper; never perfect, just good enough. It's a sensible way to make high-performance circuitry, but you can make more economical products with simple 'design rules' regarding trace size, routing, and bypass capacitors for power and ground distribution.

The three-layer Arduino layout seems to be made using design rules with wide traces and capacitors sprinkled about, but near to the expected current nodes, in its power distribution. Wide traces take up more space, but have lower electrical resistance and inductance than narrow traces. Together with (a dozen) bypass capacitors, that can keep all power deviations small enough to be ignored.

Answer 3

If the PCB is only 2 layers, you can hold it up to the light and see thru the FR-4 in those regions where there is no metal........does this Arduino have that property?

I've done 150MHz PCBs, with a mix of Schottky, CMOS, and MECL4 (four, with 0/-.4v levels) quite successfully on a 2-layer PCB, by providing a RETURN TRACE adjacent to the fast signals (MECL4 were 500pS) wherever those fast signals crossed gaps in the other layer. This was first-pass successful, but the PCB was LOW DENSITY so we had lots of routing flexibility. And our ICs were at most 16-pins flatpacks (equivalent to today's SOIC, or TSSOP).