I want to use STM32 to drive a LCM with a KS0108 controller. Sadly, it has a 6800 interface. Fortunately, ST gives a document: TFT LCD interfacing with the high-density STM32F10xxx FSMC . In p. 12 it gives two methods:

enter image description here

But the http://www.techtoys.com.hk/Displays/JHD12864J/ks0108.pdf, states when write to LCD, the data is latched at the falling edge of "E":

enter image description here

Then, assuming we use the method 1 above, the pseudo-code should like:

gpio_E = HIGH;
lcd_addr = lcd_data;
gpio_E = LOW;

After the second clause, the /CS should goes to high, and the write phase should be end. Then what's the state of the data bus, will it hold the data last output??? Or it will go to high impedance after /CS high? How can we make sure the LCM to latch the correct data?

For method 2, the situation should be similar. In ST's reference manual, it gives the timing diagram when writing:

enter image description here

When the writing phase ends, how long will we expect the data still exist on the data bus?

  • \$\begingroup\$ I'm using the FSMC to interface to an 8080 lcd. The whole module is a bit confusing. As far as I can tell, the data is not held past the end of a memory access cycle, so for the first method you would have to slow the access down, then toggle the GPIO before the memory cycle had completed. I guess you can make this work. It's probably easier to just bit-bash the interface though. \$\endgroup\$ – Jon Feb 24 '17 at 11:25
  • \$\begingroup\$ The second method should work though. Is there a reason you don't want to add the inverter gate? When the FSMC is going properly with FIFO and DMA, the whole setup is very snappy. \$\endgroup\$ – Jon Feb 24 '17 at 11:26
  • \$\begingroup\$ @Jon, please see the edited version. What if the data bus goes to high impedance at the same time when /CS goes to high? Is it reliable to use this method? \$\endgroup\$ – diverger Feb 24 '17 at 11:36
  • \$\begingroup\$ My observations were that it definitely goes high impedance at or very soon after, but it was extremely hard to see when because the bus capacitance keeps the lines in their previous state. In the end the 1 HCLK was just enough for me (in 8080 mode), and I could not find any spec for the circled part in the datasheet either. I have to do some more checks on my board this afternoon, so will see if I can spot the hold time. \$\endgroup\$ – Jon Feb 24 '17 at 11:47
  • \$\begingroup\$ @Jon: What's your test result? I'm almost decide to give up the methods ST given. \$\endgroup\$ – diverger Mar 1 '17 at 11:49

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