The answer is maybe, if you think a voltage dip in the Vcc of your chip is acceptable (and potentially having transistors enter a metastable state, which will cause unpredicted results) then don't provide decoupling capacitors.
Here is an idea of what is going on, IC's can be thought of as a variable load that switches rapidly. Sometimes entire groups of transistors switch on and off in micro or nano seconds. This can cause the load to 'source' mA in just a short amount of time. Since PCB traces (and vias) have parasitic inductance and resistance, and even though those values are small, they make a difference in the short term.
This can be modeled as a filter. In the first example (on the left) there is no cap, the chip's load decreases momentarily and the PCB trace's inductance impedes the current from Vcc, this causes a temporary drop in voltage at the load. (Oh, and there is also parasitic inductance and resistance on the ground plane for the return current but these are usually much lower because it is a plane).
In the second example, this is avoided because the cap supplies current when the voltage drops.
simulate this circuit – Schematic created using CircuitLab
I suppose there are digital IC's that may not need a decoupling cap. If the chip was placed close to the Vcc source and a the resistance of the PCB trace and inductance were minimized I suppose a decoupling cap would not be necessary.
It takes more time (and money) to figure out if a chip needs a decoupling capacitor then it would to put it on most designs, error on the side of caution and spend a few tenths of a cent and put a cap on the load.
0.1uf and 0.01uf is reasonable for most applications, microprocessors and higher current loads need multiple capacitors.