I am aware that one can easily make a divide by 2 counter for an input clock by feeding the inverted output into the input of a D Flip Flop, however,
I am tasked with the following.
Design a positive triggered D-type flip-flop (activated on the rising edge of the clock) out of gates. This means you must write a structural Verilog description of the flip-flop.
Prove to the TA that the circuit works as a divide by two counter using an oscilloscope. Use the internal oscillator and the function generator as the stimulus.
This implies the internal FPGA oscillator is the clock input and the function generator generates a square wave which must be fed in to the input of the flip flop, and the output will be the function generator frequency divided by 2. Consequently, it implies there is no feedback from the output to the input.
Is this possible with a standard positive edge triggered D flip flop?
I don't think this is possible to divide any arbitrary input signal by 2 with a fixed clock.
Since it's positive triggered, if your clock is 100MHz (changes every 5ns) and your input signal is a 500Mhz square wave (changes every 1ns), and the two signals are in phase, then the output will never be driven high because the clock will rise at the same time as the input signal.
And my code:
module PosEdgeDFF(clk, data, clr, Q, Qnot); input clk, data, clr; //clr is active low; output Q, Qnot; wire w1, w2, w3, w4, w5; nand(w1, w4, w2); nand(w2, w1, clr, clk); nand(w3, w2, clk, w4); nand(w4, w3, clr, data); nand(Q, w2, Qnot); nand(Qnot, w3, clr, Q); endmodule
And the testbench
`timescale 1ns/1ps module PosEdgeDFF_tb(); reg clk, data, clr; wire Q, Qnot; PosEdgeDFF uut(clk, data, clr, Q, Qnot); always begin #5 clk = ~clk; end always begin #1 data = ~data; end initial begin clk = 0; data = 0; clr = 0; #1; clr = 1; #80; $finish; end endmodule