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General Layout:

I've partitioned a mixed-signal board as follows:

PCB Layout

The dashed blue line indicates the analog/digital divide, but it is NOT a ground cut. This layout is intended to avoid analog and digital return currents from overlapping.

Note that one of the mixed signals ICs is an 18-bit DAC operating at 5 Volts. This means it has a voltage resolution of approximately 19 microvolts. I want to keep noise below this level to get full performance out of the chip.

Regulators

The power from VCC is immediately routed to a switching regulator. It in turn feeds various low-dropout linear regulators. Each LDO regulator is used to power either analog or digital circuitry (not both!), and is placed on the analog side or the digital side accordingly.

Questions

In order to minimize noise in the analog and mixed signal circuitry:

  1. Which side (analog or digital) should the switching regulator be placed on?
  2. If proper layout of the regulator and its surrounding caps and inductor do not allow them to fit exclusively on the correct side of the board, should a ground cut be employed? Where would the cut go?

Implementing Advice

Here's a new layout that uses the feedback I've received:

PCB Layout 2

The solid blue horizontal line is a ground cut, while the dashed blue vertical line is not. No traces run through the ground cut.

Follow Up Question

  1. Can LDO regulators be placed on the back side of the PCB opposite to the switching regulator in order to avoid wasting that space? I get the feeling that this would cause the switching regulator's noise to couple directly to the LDO outputs. If this happened it would render the LDOs' great PSRR moot and result in unacceptably noisy power lines.
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    \$\begingroup\$ First of all, you should have two grounds: Analog and Digital. And they join together on only one point: Input GND. I would make a ground plane for Digital and star or buss grounding for Analog. For switching regulators, it's always a good practice to keep the components close to each other and input side. So, you can place SREG and other LDOs on analog side close to VCC. For supplying digital ICs, draw a track (not a plane) from positive line to the IC and place a 100n close to the IC (This track [with nH of inductance] and the cap will form a nice filter). \$\endgroup\$ – Rohat Kılıç Feb 27 '17 at 19:11
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    \$\begingroup\$ @RohatKılıç: splitting the ground plane is widely considered a bad idea nowadays. \$\endgroup\$ – SharpHawk Feb 27 '17 at 19:40
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    \$\begingroup\$ Yes, @RohatKılıç is correct, Ground plane splitting is a BAD idea that causes more issues than it solves. IN particular the edges are inherently the noisiest part and any signal path that has to cross that edge is prone to issues. Further, signal return paths can also be excessively long and shared which is not good. \$\endgroup\$ – Trevor_G Feb 27 '17 at 21:27
  • \$\begingroup\$ Unless of course the circuitry of each is totally isolated... \$\endgroup\$ – Trevor_G Feb 27 '17 at 22:02
  • \$\begingroup\$ You have mentioned one central idea for a good layout, which is to avoid overlapping return current. So place and route the switching regulator such as to minimize overlapping return path with the digital and analog circuitry, and especially with the analog circuitry. With the image you posted, it would seem that the best place to accomplish that would be to put the switching regulator at the lower right hand corner. \$\endgroup\$ – rioraxe Feb 27 '17 at 22:43
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A horizontal ground cut seems like the right thing to do. In conjunction to the cut, with the regulator on the bottom left, I would try to arrange the regulator such that both the power in and out flow naturally through the right with no trace crosses the cut. I don't know what is sufficient since you are going for 19uV resolution.

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  • \$\begingroup\$ I've uploaded a new picture that I believe captures what we've discussed. I also added a new question: is it acceptable to place LDOs opposite to the switching regulator? \$\endgroup\$ – SharpHawk Feb 28 '17 at 16:40
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    \$\begingroup\$ With your objective where every little things count, I would not place the LDOs opposite to the switching regulator. Assuming you are using a buck regulator, there are two major switching current loops, one each for switch on and off. Keep track of the two loops and make them as tight as possible. Since you are placing components on the bottom, often times you can make the two loops tighter by doing that. Pack the switching regulator as tightly as possible and leave the LDOs off of that. \$\endgroup\$ – rioraxe Feb 28 '17 at 22:27
  • \$\begingroup\$ There are detours of the two loops off of the input and output capacitors. Managing the impedance of those capacitors would have an effect on your objective. \$\endgroup\$ – rioraxe Feb 28 '17 at 22:30
  • \$\begingroup\$ I'm surprised you recommended spreading the switching regulator components across two layers (to reduce loop area), I figured introducing vias would cause problems. \$\endgroup\$ – SharpHawk Feb 28 '17 at 22:58
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    \$\begingroup\$ I really do not know why vias would be a problem. I was guessing that Inductance could be the concern. It should just be another design aspect to be managed, much like a trace. With a switching regulator, often the inductor is relatively big, so inductor on one side and the other components of the loop(s) on the other can turn out nicely. That is not end of story either, for example, heat dissipation is yet another design aspect to be managed... \$\endgroup\$ – rioraxe Mar 2 '17 at 3:18
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Suppose the SwitchReg chops 1 amp at 100 nanoSeconds. Support there is a vulnerable trace, 4" away (0.1 meter) with height above the GROUND plane of 0.02" (1/2millmeter). The trace runs for 0.1 meter. How much trash will the SwitchReg induce in the trace?

$$Vinduce = 2e-7 * Area/Distance * dI/dT$$

Vinduce = 2e-7 * 0.1m * 0.0005m / 0.1m * 10^+7 amp/second

Vinduce = 2e-7 * 0.5e-3 * e+7 = 1milliVolt, or 53 LSBs.

How will you keep the SwitchReg Hfield away from the DAC? steel shields?

[edit] here is the topology:

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Can you please explain assumptions behind the calculation? \$\endgroup\$ – Gregory Kornblum Feb 28 '17 at 7:05

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