There may be a misunderstanding about what 'IP' means.
It's possible to program the fabric of an FPGA, that is the programmable LUTs and things, from the ground up. However, the bits and gates and tables in a Xilinx and an Altera are different, and are different from family to family, so it's like assembly coding a micro, they all have different low level machine code. I don't think anybody does that, at least, not commercially.
It's generally easier to use VHDL and write AND and OR and vector ADD assignments, and let the mapper turn that into LUT entries. I wouldn't call that 'IP', I'd call that compilation. When your VDHL that implies NAND gates and latches hits an Altera compiler, or a Xilinx compiler, as the fabric is different, the LUT tables will be programmed differently, but the low level function that you've described in the VHDL gets implemented the same.
If you want to use the specific hardware that Xilinx and Altera provide, like the dual port RAMs, or the 48x24 multiplier accumulator, then you need to use vendor-specific primitives. But, you have full control over how you connect to them. I still wouldn't call this IP.
If you want to use a packaged FFT, down-sampling FIR filter, or Viterbi decoder, or the embedded ARM, provided for or licensed by the vendor for their architecture, whether it's a free (with the tools) or paid-for license, that's IP.