# Clock Divider IC, Using Series or Parallel Termination

I am using a 542MILF in a design.

The datasheet says the output impedance is 20Ω (not low output impedance)

Would I have to use series termination e.i. 30Ω resistor followed by 50Ω transmission line because this IC has a fairly high output impedance?

If the clock signal is going to a HiZ input could I still use parallel termination instead?

Thanks

• What is the clock frequency and what is the length of the lines connecting it to the load? Mar 1, 2017 at 2:40
• ~100kHz. The trace will be as short as possible <1".
– Tony
Mar 1, 2017 at 2:50
• 100 kHz and 1 inch you don't need to worry about impedance matching or transmission line characteristic impedance. Mar 1, 2017 at 2:51

The datasheet is quite clear.

Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω.

First I need to correct your assumptions.

20Ω typ is the lowest impedance in 5V CMOS logic drivers in existence.

• Most 3.3V Logic is 25Ω and 5V logic is around 50Ω.
• effective Z tolerance over temp and supply range is around 50% , Vol/Iol=Z

Note that this chip has a 1ns (typ) rise time and max skew of 500 ps and 1" was recommended max for path length for best performance.

## What does this mean?

It means signal integrity of clocks degrades as path length increases beyond this without impedance matching but is preserved with matching.

Transmission Line Rules for impedance matching become important when the risetime , Tr is < 15% of the propagation delay. i.e. Wavelength is $\lambda =~0.35/Tr$ thus if Tr is greater than 5% of a $\lambda$. Others use 10% as a rule of thumb with less margin on signal integrity.

Otherwise inductive tracks with distributed capacitance can cause overshoot and ringing. Parallel Loading can reduce the Q and decay time.

A true matched impedance with stripline and termination resistor is the ideal scenario at the expense of 50% reduced Vpp swing.

Obviously compromises can be made between ringing and load impedance if you know the level of ringing, but usually this is not needed as terminations can be split from Vcc to gnd to maintain proper bias around input thresholds.

Essentially these rules of Transmission Line design apply to all CMOS for rise time vs path length when these rules need to be applied. This is because is the rise time from higher output impedance drivers with higher load capacitance results in lower slew rates, longer path lengths can be used without terminations using careful controlled impedance tracks.

Microstrip:                    Stripline.:
Zo= 60-70 Ohms for w/h = 1,    0.6 times that of microstrip.
40-50 ohms for w/h = 2.    0.6 times that of microstrip.
Propagation Delay: 150 pS/in   180 pS/in
Average Propagation Delay: 2 nS/ft  between microstrip and stripline.
(Ref Henry Ott)