Here is a verilog code: (This code is not for synthesis)
`timescale 1 ns / 1 ns module test; reg r1, r2, r3, r4; reg clk_at_time, clk_from_clk; // Initialize signals initial begin r1 <= 1; r2 <= 0; clk_at_time <= 1; #200 $finish(); end // Generating simple a clock (period time is 10ns) (as expected) always #5 clk_at_time <= ~clk_at_time; // Generating a clock based on the clk_at_time. // This clk_from_clk is always equals the clk_at_time (as expected) always @ clk_at_time clk_from_clk <= clk_at_time; // r1 and r2 inverted at all posedge event. (as expected) // r3 is constant 0 (as expected) always @(posedge clk_at_time) begin r1 <= r2; r2 <= r1; r3 <= clk_from_clk; end // r4 is constant 1 ???!!!??? HOW ???!!!??? always @(posedge clk_from_clk) begin r4 <= clk_at_time; end endmodule
In the code there are two clock: first is the traditional clock generated by time
always #5 the second is generated by this clock
always @ clk_at_time The two clocks are always equal (as expected)
The strange thing that if I use the clk_from_clk in clk_at_time's block the previous value will be used of clk_from_clk. (OK), BUT if I use the clk_at_time in clk_from_clk's block the NEW value will be used of clk_at_time.
See the waveform:
clk_at_time are equals always.
r4 are analog:
clk_at_time's block and driven by
clk_from_clk's block and driven by
clk_at_time are really the same
r4 should have be equal always. BUT See the waveform:
r3 is always 0 and
r4 is always 1
HOW? What is the rule?