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Let´s assume I use a synchronous buck converter switching at 1MHz and a 47µF MLCC at its output whose self-resonance frequency is right at 1MHz.

For my understanding, using an DC/DC converter output capacitor near or at its self-resonance frequency is not a bad idea. But I am not sure. I think, there should not be instability issues as long as the resonance frequency of the inductor/capacitor combination is well above or below the 1MHz. So, for 47uF and 2.2µH, I have resonance near f = 15kHz, which should be fine.

Is the "loss" or even "turnover" of the phaseshift of the capacitor a problem in that situation? I should note, that the converter uses constant frequency PWM and (as far as I can deduce from the block diagram below) peak-current mode control.

enter image description here

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I think, there should not be instability issues as long as the resonance frequency of the inductor/capacitor combination is well above or below the 1MHz.

Stability depends mainly on the behavior of the circuit within the bandwidth of the control loop and slightly above. As another answer says, a key parameter is the phase margin of the control loop. This is measured at the frequency where the open loop gain passes through unity.

This frequency is generally much lower than the switching frequency of the regulator, typically by as much as 10x, so about 100 kHz in your example (but read your datasheet and analyze your design to figure out what it is in your particular circuit).

Edit: I should add, the output capacitor is also important to smooth the ripple from the switching waveform. This is a separate issue from the stability of the control loop. As another answer says, the switching waveform will contain harmonics far above the fundamental frequency, so you will likely want to include some lower value, higher SRF, capacitors in parallel with your 47 uF MLCC to deal with those components.

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It's fine for frequencies below 1 MHz but, because the PWM is a fast switching waveform, there will be harmonics all the way up to several hundred MHz. Those harmonics that are higher than the capacitors series self resonant frequency will progressively be less attenuated.

This could mean a noisy output voltage and one that emits EMI.

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  • \$\begingroup\$ Ok, so the circuit should work fine from a stability point of view, regardless of the exact control scheme? EMI is another story, that could be handled by paralleling smaller caps and or a series ferrite. \$\endgroup\$ – Junius Mar 2 '17 at 15:50
  • \$\begingroup\$ It could become unstable because you are feeding high frequency crap into the feedback circuit and this is not what is expected. There is no generic answer other than don't do it! \$\endgroup\$ – Andy aka Mar 2 '17 at 15:55
  • \$\begingroup\$ Ok, but isn't the "HF-crap" that is inserted into the feedback loop at a minimum in this case (beside of the phase shift aspect)? Another capacitor is likely to have a bigger impedance right at the fundamental switching frequency. And as I sad, smaller caps that have low impedance for the harmonics are needed in any case. That does not really influence the choice of the "main" output capacitor(s)? \$\endgroup\$ – Junius Mar 2 '17 at 16:04
  • \$\begingroup\$ No, if your capacitor is self resonant at 1 MHz then it fails to be effective at higher frequencies because it becomes an inductor and doesn't filter the crap. Think about it for a while or do a sim. \$\endgroup\$ – Andy aka Mar 2 '17 at 16:31
  • \$\begingroup\$ Yes, i comfirmed your point already that the capacitor is not effective FOR THE HARMONICS, but it should be for the fundamental frequency, that was the point in my last comment.. \$\endgroup\$ – Junius Mar 2 '17 at 16:36
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The critical selection criteria must consider both ripple attenuation of impedance ratios of (ESR + Xc) with (DCR + XL) but also the phase margin.

The phase margin should be at least 45 degrees to avoid substantial ringing after transient loads. The Q at the crossover frequency ought to be reduced to avoid large phase excursions. If your SRF is too low relative to the switching frequency then phase margin will be compromised. Higher ESR can ease this which reduces Q and improves phase margin at the expense of more ripple.

Here is an example of what I meant.

Note the SRF at 1MHz has no bad effect on the response to 1MHz but the choice of 47uH now with a 2uH choke causes a serious resonance near 37KHz with a gain of 20dB and thus very poor phase margin with the resulting high Q of 10.

enter image description here

Thus the value of LC and the Q determined by X(f)/(DCR+ESR) ratio are far more critical than the SRF of C.

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  • \$\begingroup\$ Ok! Could you give me an advice on how to estimate the capacitor that meets a given phase margin? I honestly don't know how to setup equations for the control loop. it should be possible when the internals of the regulator are known, but the datasheet does not elaborate on the internal compensation details.. \$\endgroup\$ – Junius Mar 2 '17 at 16:43
  • \$\begingroup\$ look on other app notes then \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 2 '17 at 17:37

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