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this is the error: Error (10500): VHDL syntax error at Bin7SegDecoder.vhd(15) near text "when"; expecting ";"

It may be simple but I don't know what's the error. Thanks in advance!

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Bin7SegDecoder is
    port( enable   : in  std_logic;
            binInput : in  std_logic_vector(3 downto 0);
            decOut_n : out std_logic_vector(6 downto 0));
end Bin7SegDecoder;

architecture Behavioral of Bin7SegDecoder is
begin
    process(binInput, enable)
    begin
        if (enable = '1') then
            decOut_n <= "1111001" when (binInput = "0001") else --1
                            "0100100" when (binInput = "0010") else --2
                            "0110000" when (binInput = "0011") else --3
                            "0011001" when (binInput = "0100") else --4
                            "0010010" when (binInput = "0101") else --5
                            "0000010" when (binInput = "0110") else --6
                            "1111000" when (binInput = "0111") else --7
                            "0000000" when (binInput = "1000") else --8
                            "0010000" when (binInput = "1001") else --9
                            "0001000" when (binInput = "1010") else --A
                            "0000011" when (binInput = "1011") else --B
                            "1000110" when (binInput = "1100") else --C
                            "0100001" when (binInput = "1101") else --D
                            "0000110" when (binInput = "1110") else --E
                            "0001110" when (binInput = "1111") else --F
                            "1000000"; --0
        else
            decOut_n <= "1111111";
        end if;
    end process;
end Behavioral;
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  • 2
    \$\begingroup\$ Turn on your compiler's VHDL-2008 option. This form of conditional expression was only allowed outside a process in earlier revisions of the language. \$\endgroup\$ – Brian Drummond Mar 2 '17 at 20:32
  • \$\begingroup\$ I already did that and it still gives me that error :( \$\endgroup\$ – João Mar 2 '17 at 21:10
  • \$\begingroup\$ Well the code compiles fine for me ghdl -a --std=08 bin7segdecoder.vhd (in ghdl 0.34-dev) so you may have to check the quality of your simulator's VHDL-2008 support or upgrade to a better simulator. \$\endgroup\$ – Brian Drummond Mar 2 '17 at 22:23
1
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You are trying to use a concurrent when-else assignment clause in a sequential process.

You can move the assignment out of the process and modify the 'when' clause to first test for enable = '0' before all the 'when' tests on binInput.

Or you can stick with a process and change the when-else clause to a case statement and decode that way. This is shown below and is a clearer expression than the process.

library ieee;
use ieee.std_logic_1164.all;


entity Bin7SegDecoder is
  port(
    enable                        : in  std_logic;
    binInput                      : in  std_logic_vector(3 downto 0);
    decOut_n                      : out std_logic_vector(6 downto 0)
  );
end Bin7SegDecoder;


architecture Behavioral of Bin7SegDecoder is
begin


  decOut_n   <=   "1111111"  when (enable   =  '0')
            else  "1000000"  when (binInput = X"0")
            else  "1111001"  when (binInput = X"1")
            else  "0100100"  when (binInput = X"2")
            else  "0110000"  when (binInput = X"3")
            else  "0011001"  when (binInput = X"4")
            else  "0010010"  when (binInput = X"5")
            else  "0000010"  when (binInput = X"6")
            else  "1111000"  when (binInput = X"7")
            else  "0000000"  when (binInput = X"8")
            else  "0010000"  when (binInput = X"9")
            else  "0001000"  when (binInput = X"A")
            else  "0000011"  when (binInput = X"B")
            else  "1000110"  when (binInput = X"C")
            else  "0100001"  when (binInput = X"D")
            else  "0000110"  when (binInput = X"E")
            else  "0001110";   -- (binInput = X"F")


end Behavioral;
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  • \$\begingroup\$ Can you help me do that please? \$\endgroup\$ – João Mar 2 '17 at 22:49
  • \$\begingroup\$ Yes, will post it \$\endgroup\$ – TonyM Mar 2 '17 at 23:02

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