# Level shifting of 125 MHz clock signal

I have 3.3V 125MHz clock signal which need to be translated down to have an amplitude of 1.8V. My first idea was to use some logic inverter, run it on 1.8V, and since it probably has protection diodes on its input everything should be fine. I have found a nice model from TI, SN74LVC1G04-Q1. In the product details, it is written max frequency at nom. voltage is 150 MHz. Does this mean 150 MHz of square signal, or the highest frequency component?

Besides buying a logic inverter I was also thinking of making a discrete inverter or even use a simple transistor switch. So my questio is basically, which direction should I go?

• Logic gates are specced for logic signals, it is for square-ish signals. There are special chips made for buffering clocks : PLLs, zero-delay buffers... Mar 5, 2017 at 1:17

For reducing the clock voltage from 3.3V driver to 1.8V at receiver, you can simply use a resistor divider, properly designed for your trace impedance.

Even more, you just need to put a trace impedance-matching load at the receiver end of clock trace, and the voltage amplitude will come down naturally.

I would recommend to use the free LTspice tool to model your source, trace (transmission line), and input pin model to get proper resistors and tune up the network for nice-looking clock.

The easiest way to do this is with a buffer that allows downtranslation and is fast enough.

The maximum frequency depends on the supply voltage. At 1.8 V, LVC devices are specified for only 70 MHz, so you cannot use this inverter.

The only logic family that is fast enough at 1.8 V is AUC (see figure 1 of this application note), so look at the SN74AUC1G125 (or the SN74AUC1G04 if you really want an inverting buffer, but only the '125-EP is available for higher temperature ranges).

If a device has a protection diode from its input to VCC, then there is no limit on the current that can flow through this diode, unless you add a serial resistor (which can slow down the signal). So you need a device without such a diode. Neither LVC nor AUC have such a diode; they were designed this way in order to allow downtranslation.

• In provided application note is stated that AUP1T can be used only for 3.3 V up to 160 MHz. In TI's website for AUP1T inverter, it is stated Fnom: 1.8V, 2.5V, and 3.3V. F @ Vnom = 190 MHz. Whom should I trust and what is nominal voltage in this case? Are maybe AUP1G and AUT1G identical concerning speed? Mar 6, 2017 at 8:50
• When downtranslating, you are not using a 3.3 V power supply. And AUP and AUC are different logic families.
– CL.
Mar 6, 2017 at 10:23