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My first PCB made with KiCad. I have some specific questions about my design. First I was not sure of this would have been another down-vote magnet but this article encouraged me to post this.

  1. Capacitor placement; should C2 be connected to the ESP pins directly in stead of the front and back plane? It is supposed to be a decoupling capacitor.

  2. Should I redraw sharp corners in a trace like on the back plane near pin 4.

  3. What is the downside of using GND as back plane and VCC as front plane in stead of using traces only. It's a lot of surface, it does not feel right to just 'power' the entire front and back of the PCB.

Note: P4 is for input power to the board and the board will not be used for programming the ESP, just for continues use with deep sleep enabled.

Please add a comment when you down vote, I am here to learn.

All the data is on GitHub, in case you need it.

circuit front back

UPDATE
Added a better regulator, added a capacitor, added two mounting holes, removed the VCC field from the front, removed the crazy via's, moved some parts around and used the space below the components for traces.

enter image description here

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    \$\begingroup\$ Do you want mounting holes? The tracks on the LHS of the board seem very thin. \$\endgroup\$ – skvery Mar 5 '17 at 11:27
  • \$\begingroup\$ Mounting holes is a good idea! I will add those. \$\endgroup\$ – Thijs Mar 5 '17 at 15:10
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    \$\begingroup\$ When designing a PCB DO not be afraid to run signals under components. You can think of them as another layer if you like. For example the two resistors top left could have been oriented vertically instead of horizontally, "Jumping" the lines to pins 1 & 2. It would thus have saved you two feed-throughs \$\endgroup\$ – Trevor_G Mar 5 '17 at 15:42
  • \$\begingroup\$ Confirm no holes for pin 17 to 22 \$\endgroup\$ – skvery Mar 6 '17 at 6:16
  • \$\begingroup\$ Yes, that is by design, I'm not sure why the other ESP pins do have holes. Maybe for bottom side traces? \$\endgroup\$ – Thijs Mar 6 '17 at 7:13
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Capacitor placement; should C2 be connected to the ESP pins directly in stead of the front and back plane? It is supposed to be a decoupling capacitor.

I'd call C2 a "stabilizing" capacitor; I'd put it close to the power IC (U3) and have a smaller ceramic cap (100nF) close to the VCC pin of the ESP. I don't understand why you chose a point that is both far from the power source and from the VCC pin – that's a) not very good for its intended purpose, and b) makes it harder to route.

Should I redraw sharp corners in a trace like on the back plane near pin 4.

no. That question comes up rather often. Corner shapes mattering to a signal or power line is, for anything short of microwave frequencies, an urban myth.

What is the downside of using GND as back plane and VCC as front plane in stead of using traces only. It's a lot of surface, it does not feel right to just 'power' the entire front and back of the PCB.

Using a ground plane is a common thing to do. It improves the resilience of your board against EM interference, and generally looks pretty neat.

It's not that common to have a power plane. Basically, don't – if you use a plane, it's usually going to be GND. You can have a GND plane on both top and bottom layers – but you don't have to. In fact, out of lazyness, and because it actually doesn't do any good, I'd not have a fill on the top layer of your board. Having one on the bottom isn't the worst idea, though.

Comments?

Yeah. How much power do you really need? The 3.3V regulator, from the footprint, looks a bit oversized (but might very well be the cheapest you personally can get, so go for it if it is).

You can rotate R2 by 180° to make the trace from R to LED easier :)

You can use R4 as a "bridge" over the REST/ADC lines to avoid the awkward "going to the bottom, coming back above the ESP" thing you do.

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  • \$\begingroup\$ Another comment: use thicker traces. There's no reason to use such thin traces if you have room. \$\endgroup\$ – Vladimir Cravero Mar 5 '17 at 13:41
  • \$\begingroup\$ Thanks, I will update my design! The trace width may be the default from the OSH Park KiCad template I use but I'll check if I can broaden them. I will also check for a better suited regulator, I will read the ESP12 datasheet for the max power consumption. \$\endgroup\$ – Thijs Mar 5 '17 at 15:12
  • \$\begingroup\$ I totally disagree with "Corner shapes mattering to a signal or power line is, for anything short of microwave frequencies, an urban myth." When it comes to noise emission it's all about signal rise time, not frequency per say. If the signal is even a pretty low frequency clock, and has a sharp rise and fall time, the harmonics generated can and will be exaggerated by a sharp corner like that. It's also quite unnecessary in this design.. switch the feed-throughs left-right. \$\endgroup\$ – Trevor_G Mar 5 '17 at 15:38
  • \$\begingroup\$ that isn't completely true. Yes, if you "fold" your trace into a coil, it will add inductance and thus have all kind of undesired effects. "when it comes to noise emissions it's all about signal rise time" doesn't even make sense. Please do the math on how much rise time (relative to signal period) is increased for non-microwave frequencies. I do agree that for a broadband signal (e.g. a clock), having an inductance in line is a bad thing, no questions asked, but you'll see that this hardly matters for clocks <100 MHz at all.You can build perfectly horrible antenna traces with nice rounds,too! \$\endgroup\$ – Marcus Müller Mar 5 '17 at 19:11
  • \$\begingroup\$ @Trevor I do, however, agree on this sharp bend being totally unnecessary. \$\endgroup\$ – Marcus Müller Mar 5 '17 at 19:12

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