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I'd like to route a single clock signal to one of several possible destinations by means of a few (2 or 3) address select lines.

Background: I'm driving 595 shift registers from a microcontroller (Arduino for now, possibly ESP8266 later). I want to have multiple (probably 4, possibly 5 or 6) separate chains of SRs that can be driven separately, so that I can (for example) drive 14 segment displays on each chain, and scroll (shift) each separately. My original design had all of the SR chains sharing \$\text{SER}\$, \$\text{RCLK}\$, and \$\text{SRCLK}\$ lines from the microcontroller, and using a 3-8 decoder to drive the \$\overline{\text{SRCLR}}\$ as a sort of "Chain select". However, I realized that \$\overline{\text{SRCLR}}\$ also clears the input registers, which would ruin the ability to scroll the outputs... I'd need to "refill" each SR chain after its \$\overline{\text{SRCLR}}\$ was low.

My next idea was to use a separate \$\text{SRCLK}\$ for each SR Chain. Option B of this ESE answer suggests the same approach. As long as \$\text{SRCLK}\$ doesn't change, any signals on \$\text{SER}\$ won't change the input registers and any change on \$\text{RCLK}\$ will re-latch the same data to output. However, I don't want to have multiple physical pins for the multiple clocks because (a) pin count constraints, and (b) I'll probably use the Hardware SPI port to send data to the SR chains.

Which leads me to the question. Assuming I have a single clock pin (output) from the microcontroller, how can I send that signal to only 1 of several possible destinations? Assume 3 address lines driving a 3-8 decoder, giving me 8 "SR Chain Select" signals. I'm considering using an AND gate for each SR Chain, with the clock as an input to each, and the 8 Chain Select signals as the other input to each (ignoring for now that most 3-8 decoders output 7 highs and 1 low, so I'll likely need an inverter on each decoder output line). See schematic below (only 4 AND gates shown for reduced size). Is this the best solution, or is there a better approach?

schematic

simulate this circuit – Schematic created using CircuitLab

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What you are looking for is something like a 74(HC)138 or 238 . The difference is that the 138 unselected outputs are high and the selected low, while the 238 has unselected low and selected high. In both cases the IC has, in addition to the 3 address lines, 3 select lines, one of which you can use as your clock input.

schematic

simulate this circuit – Schematic created using CircuitLab

Note that you'll have to be careful. If you change your address lines while the clock is high, you'll get a rising edge on tbe newly-selected output.

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Most 3->8 decoders have a data (or enable) input, feed the clock to that and you don't need the extra AND ports.

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A simpler way to do this is via a demultiplexer. This takes one input and routes it to 1 output based on an input address.

https://en.m.wikipedia.org/wiki/Multiplexer

One word of caution: make sure the multiplexer you choose can handle your clock speed!

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