For a 4-bit signed full adder, the output range in decimal is -8 to +7. I created a 4-bit signed full adder in verilog and simulated it. When I added +5 and +3, I got a sum of -8 and overflow=1. This should be correct right? When I added +3 and -1, I got a sum of +2 and a carry of 1. Is this correct or is my code wrong?