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Output Characteristic Schematic single stage enter image description here

Hi guys, I've been trying to design a simple amplifier with some gain. My first question is, why are there multiple output characteristic graphs (2 shown) for a single JFET? My first step in designing an amplifier/switch is to usually get some Quiescent (Q-pt) point based from the datasheet graphs. However, with this case, I don't know which graph should I use. Is Vgs,off device specific or is it also affected by the Quiescent point? The datasheet shows that Vgs,off is between -3v(typical) to -8v (maximum).

I also want to know if I am doing the right steps in my design. In my case, I want to make two single stage each with around 10x gain to get an amplifier with around 100 gain. I am not as good in designing using FET's compared to using BJT's honestly. In fact, this is my first time using a JFET, but from what I understand, they are very similar to MOSFETs, only that this time, -Vgs (instead of +Vgs) is applied, and controls the width of the channel (ie controlling Id). So here are my steps roughly for designing just the single stage. I am using the graph for Vgs,off = -3v.

1.) Choose some Q-pt on the output characteristic.

2.) Let's say I choose some biasing pt. Since my Vcc = 12, I would roughly want my Vds to be around 4 to 10v to make sure that my JFET is in saturation region, while having some room for swing. My input AC is 20mVpp, so with my target gain of 10 for one stage, I am expecting an output of around 200mVpp. Say I get this Quiescent point: Vds = 6v and Vgs = -0.3v. From my little research, I came across this formula: Id = Idss(1-(Vgs/Vgs,off) which is applicable for JFET in saturation. Idss in this case is around 10.5v (midway of 12 and 9v) since Idss is the max current that can flow when Vgs = 0. However, I didn't used this formula and instead, just used datasheet with some visual estimation since I believe the equation above is just a rough estimation that doesn't take into account the effect of Vds(which is less compared to Vgs, when JFET is in saturation). Going back to my calculation, visual estimation would tell me that for Vds = 6v, Vgs = -0.3v, then Id ~ 8mA. So now, I can get the restriction on Rs + Rd. Via KVL, Vcc = IdRd + Vds + IdRs. Since Ig ~ 0, then Is = Id. So 12v = (8mA)(Rd+Rs) + 6v -> Rd+Rs = 750ohms.

3.) Now, I got to take into account the gain that I want, the small signal gain that is. Approximately, Av = -gm(Rd//ro) assuming ro >> Rd. I also came across this assumption very often from what I read. So Av = -gmRd. I came across a formula, gm = (-2Idss/Vgs,off)(1-(Vgs/Vs,off)). For other case, I used visual estimation using the Vgs vs Id curve (3rd figure) by trying to draw a tangent line at my quiescent point and getting Id/Vgs = gm. But since the only Vds vs Id curve on the datasheet is for Vds = 10v, I decided to use the formula whenever my chosen Vds /= 10v like in this case. In this case, gm = 6.3x10^-3 S using the formula above. I can now compute for Rd. Rd = (Av)/(-gm) = (10)/(-6.3x10^-3) = 1587ohms. This is in contradiction with what I got above since Rd + Rs = 750ohms and my computed Rd is greater than this. I try to choose another Q pt then. Note that most of my calculations led to this case, so I was thinking that I am missing something here. Any help would really be appreciated but my priority is knowing how to get the Vgs,off exactly, so I can at least know which graph to use. (which is a problem if Vgs,off is actually -8v for example, since the datasheet only shows output characteristics for -2 and -3v).

Additional: Assuming I didn't get the problem above, here are my next steps 4.) Assuming I got Rd < Rd + Rs, I could get the value of Rs then.

5.) I now have to decide the values of R1 and R2 to get the Vgs I need. Vgs = Vg - Vs. Vg = Vcc(R1/(R1+R2) = 12(R1/(R1+R2)). Vs = IdRs. So Vgs = Chosen Vgs = -0.3v = (12R1/(R1+R2)) - (8mA)(Rs). I will then set some value for R1 then solve for R2.

This should finish my calculation for the components (well resistors at least).

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    \$\begingroup\$ While the images from the datasheet are helpful, a link to the datasheet would be useful as well. \$\endgroup\$
    – Null
    Mar 6 '17 at 17:02
  • \$\begingroup\$ The difference in the two charts you show first are that the left one if for a device with Vgs = -2 and the right hand one for a Vgs = -3. The FETs you buy have a range of Vgs values unique for every device. \$\endgroup\$ Mar 6 '17 at 17:03
  • \$\begingroup\$ oh, so I need to conduct an initial experiment to actually get the Vgs,off of my device? Link to datasheet btw: www2.eng.cam.ac.uk/~dmh/ptialcd/jfet/2N3819.pdf \$\endgroup\$
    – user139731
    Mar 6 '17 at 17:04
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    \$\begingroup\$ Either that or implement a design that is as less \$V_{GS,\ off}\$-dependent as possible. \$\endgroup\$ Mar 6 '17 at 17:07
  • \$\begingroup\$ Very approximately your gain is Rd/Rs, if you want to use gm to calculate the gain, then it's simpler to bypass Rs (it's then only for defining the DC bias). You could read this: whites.sdsmt.edu/classes/ee320/notes/320lecture31.pdf or dozens like it to get more information. \$\endgroup\$ Mar 6 '17 at 17:07

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