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I have the following circuit, the top is a PMOSFET, bottom is NMOSFET

enter image description here

I'm having troubles understanding what exactly is happening here. I've dealt with PMOSFETs and NMOSFETs separately, and here combined, it seems as though I have no idea as to how to approach this.

Let's say I ground \$V_{\text{in}}\$ (=0), then is the difference in voltage from \$V_{\text{in}}\$ to the top of the PMOS 2.5V? and vice versa with the NMOS? How does that affect \$V_{\text{out}}\$ and the rest of the currents running through the circuit?

I'm not looking for answers, but rather, a way to understand what goes on here.

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  • \$\begingroup\$ It sounds like you actually haven't internalized the very basic idea of potential difference. Yes, if one node is at 0 V (relative to "ground") and another is at 2.5 V, the difference between them is 2.5 V. \$\endgroup\$
    – The Photon
    Commented Mar 6, 2017 at 18:57
  • \$\begingroup\$ When I say "basic" I mean it's important to understand this in order to understand just about everything else in EE, not "you're dumb if you don't understand it". \$\endgroup\$
    – The Photon
    Commented Mar 6, 2017 at 19:06
  • \$\begingroup\$ Look at it separately. Because what activates one, dactivates the other. It is an invertor. \$\endgroup\$ Commented Mar 6, 2017 at 19:48
  • \$\begingroup\$ Wow. This looks like a NOT gate ;) \$\endgroup\$
    – user103380
    Commented Mar 6, 2017 at 20:07
  • \$\begingroup\$ It not a NOT gate because the gnd is not at 0V but at -2.5 V ! \$\endgroup\$ Commented Mar 6, 2017 at 22:48

2 Answers 2

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inverting amplifier

To understand what is happening it is better not to apply a static voltage to \$V_{\text{in}}\$ but instead a Sinus

Think about what is happening while the Voltage is rising from 0V to peak (The n-Mosfet is "opening" as the voltage is rising and so your \$V_{\text{out}}\$ is getting more "Negative)

And than again what is happening while the Voltage is falling (Now the p-Mosfet is doing the same thing as previously the n-Mosfet and the n-Mosfet is now "blocking" the negative Voltage)

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Look at the loadlines, for NMOS and for PMOS

schematic

simulate this circuit – Schematic created using CircuitLab

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