I'm working with the ADC on STM32L476RG. I found that the SAR used for the ADC is 12 bit whereas the data register (ADC regular Data Register (ADCx_DR)) is 16 bit (16 bit reserved). Why is it like this? Will the higher (MSB) 4 bits always be zero?

  • \$\begingroup\$ @Colin__s suggest you post this comment as an answer, so the question can be closed. \$\endgroup\$ – Jon Mar 8 '17 at 10:54
  • \$\begingroup\$ @Jon have done. \$\endgroup\$ – Colin Mar 8 '17 at 10:55

You are able to select an alignment within those 16 bits, if you want the ADC data to be in the most or least significant bits.

If it's right aligned bits 15:12 will be 0, or the sign if it's signed data. It's documented in section 18.4.26 of the linked reference manual.

  • \$\begingroup\$ What is the use of these left and right alignment? \$\endgroup\$ – Arun Joe Mar 9 '17 at 7:26
  • \$\begingroup\$ The data you acquire from the ADC generally be used/processed by something else. It gives you the option of the hardware placing the data in the appropriate place within a 16bit word without you having to shift it using processor clock cycles. An example would be if you were to feed it out via I2S to a DSP, that part may have a requirement that the data coming in is left aligned. \$\endgroup\$ – Colin Mar 9 '17 at 7:56

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