I was looking at the solution for a homework posted here:
and noticed that for 1.1, it didn't include the Register file latency for the write-back part. I know that after the last Mux, the processor should write the result from this Mux back to the Register file as specified by the destination register Rd.
I checked some more sources online and they're all doing the same thing, not just for ADD, but also for the LW instruction. Why is it not included in the clock cycle time computation?