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I was looking at the solution for a homework posted here:

https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf

and noticed that for 1.1, it didn't include the Register file latency for the write-back part. I know that after the last Mux, the processor should write the result from this Mux back to the Register file as specified by the destination register Rd.

I checked some more sources online and they're all doing the same thing, not just for ADD, but also for the LW instruction. Why is it not included in the clock cycle time computation?

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If I recall correctly, and to be clear this is architecture dependent, it's relatively common design practice that the register are designed to write on one clock edge and read on the opposite clock edge. So that write latency is kind of background-ed in the execution timeline.

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  • \$\begingroup\$ Isn't that supposed to happen when the processor is already pipelined? i.e. the positive edge is allotted for one instruction's WB stage, and the negative edge is for reading the registers (ID) for another instruction. I think they're trying to compute the clock cycle time for a single-cycle processor, not the pipelined one. \$\endgroup\$
    – Gabriel
    Mar 9, 2017 at 0:20
  • \$\begingroup\$ Whether the processor uses single cycles or is pipelined, only instructions that depend on the results of a preceding instruction will need to wait for the results to be written to a register, and even then it's often feasible for the processor to forward the results to dependent instructions without waiting for them to be written to the register file or to memory, depending on how many instructions come between them. \$\endgroup\$
    – Charles B. Cameron
    Jun 21, 2022 at 23:57

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