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My setup: 53 x 28 mm PCB, uC will run somewhere between 1 MHz and 8MHz. Dual layer PCB design.

From the info I gathered on this site it seems there are two aspects to consider in deciding how to treat the PCB traces:

1) Maximum sinusoidal frequency of the digital (square) signals running on the board. For this one I understand that the 3rd harmonic is a good maximum frequency to be weighed in.

2) Rising / falling edges of such digital signals. For this point I do not know what frequencies needs to be considered or how to determine them. Or how to manipulate (?) them either.

I am not sure whether or not my understanding is flawed. All I could find in the datasheet of the ATMega168 uC is that for some pins used in some modes (such as TWI) the hardware switches to a special mode that won't consider glitches shorter than 50 ns and that it slows down its the slew rate on those pins.

Help!

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    \$\begingroup\$ Compare the wavelength of 8 MHz - and its 5th or 7th harmonic - with the length of your PCB. \$\endgroup\$
    – user16324
    Commented Mar 8, 2017 at 11:37

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When considering traces as transmission lines for digital signals, switching frequency does not matter.

Forget about your MHz. Or kHz.

Only slew rate matters.

Detailed explanation:

A driver is connected to a transmission line. It switches from 0 to 1 in a time T. The waveform propagates along the transmission line, reflects at both ends, and the original signal combines with its reflections at the receiver.

If the edge transition time is shorter than the time it takes for the reflections to dampen, then the received signal can contain errors, no matter its frequency. Even if it is a 1kHz clock to a shift register, if the edges are doubled, then your shift register will shift two bits instead of one.

This is the first signal integrity aspect. Check your part datasheet for slew rate, or measure it with a scope. It's a quite slow microcontroller, unlikely to be equipped with super-fast IO buffers. Your board is small. You should be absolutely alright IMHO.

The second integrity aspect is ringing, due both to reflections and LC interaction between trace and pin capacitance. Having IO buffers with lower drive strength dampens it. Your uC datasheet mentions something like 10-20mA drive strength, so output resistance is not negligible. It should dampen it.

In other words, you shouldn't worry unless you're driving cables.

PS: Don't forger about EMC and grounding.

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    \$\begingroup\$ Isn't it a bit misleading to say that "frequency does not matter"? Aren't the high frequency components of the square signal / edges exactly whats of interest here? Its just not the base frequency of the square wave that matters, but its harmonics. \$\endgroup\$
    – Rev
    Commented Mar 8, 2017 at 12:51
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    \$\begingroup\$ I added "switching frequency" to make it explicit. \$\endgroup\$
    – bobflux
    Commented Mar 8, 2017 at 12:55
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    \$\begingroup\$ I think what he meant @Rev1.0, is that even a low frequency signal can and will have VERY high frequency harmonics if is has a fast rise time. Event a single trigger pulse once a second will generate some RFI / Cross-coupling / Ringing effects if it is sharp enough. \$\endgroup\$
    – Trevor_G
    Commented Mar 8, 2017 at 15:23
  • \$\begingroup\$ Yup. Send a slow (frequency) signal from a driver with fast edges into a cable without proper termination, you'll get messed up edges at the other end. Had a JTAG adapter produce random double clocking because of this. \$\endgroup\$
    – bobflux
    Commented Mar 8, 2017 at 15:37
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    \$\begingroup\$ The switching frequency has a lot to do with how much you can slow down the edges and still have the system work. \$\endgroup\$
    – The Photon
    Commented Mar 8, 2017 at 17:05

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