My setup: 53 x 28 mm PCB, uC will run somewhere between 1 MHz and 8MHz. Dual layer PCB design.
From the info I gathered on this site it seems there are two aspects to consider in deciding how to treat the PCB traces:
1) Maximum sinusoidal frequency of the digital (square) signals running on the board. For this one I understand that the 3rd harmonic is a good maximum frequency to be weighed in.
2) Rising / falling edges of such digital signals. For this point I do not know what frequencies needs to be considered or how to determine them. Or how to manipulate (?) them either.
I am not sure whether or not my understanding is flawed. All I could find in the datasheet of the ATMega168 uC is that for some pins used in some modes (such as TWI) the hardware switches to a special mode that won't consider glitches shorter than 50 ns and that it slows down its the slew rate on those pins.