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I saw many videos on YouTube in which people delid processors and then apply better liquids for cooling the processor. Example: i5 & i7 Haswell & Ivy Bridge - FULL Delid Tutorial - (Vice Method)
However I also saw that people working in fabs are wearing special costumes, because the silicon wafers are extremely sensitive to all kinds of particles.
What actually happens when delidding a processor?
Wafers are extremely sensitive during manufacture, because if any dust or dirt particle settles on it between any process steps, then the following process steps will fail on the contaminated spot.
Once manufacture is finished, and the chip receives its last layer, dust will no longer bother it.
I would venture a guess that desktop CPUs which have thermal spreading lids on them will receive a proper surface treatment for application of the chosen thermal paste.
Something not mentioned by the other answers is that it's not only the chip itself that's so sensitive to dust. It's also the lithography plates used to print the resist layers for each stage of the process.
Image from Wikipedia
Incredibly advanced optics are used to project light through these essentially "film negatives" onto the resist layer on the wafer. These negatives are several times larger than the actual features to help reduce the effect of error in the plate, but feature size is only around 4-5x larger. The UV light is shown through them, and focused down to the appropriate dimensions to expose the resist at the appropriate resolution. With current process technology reaching down to 10nm, these litho plates have to be "perfect" because they rely on diffraction techniques to print features many times smaller than the wavelength of light used. If a spec of dust were to get on one of these plate, it would ruin every chip subsequently printed with that area of the litho plate.
A passivation layer is the final step, excluding the atmosphere. This layer is formed by exposing the wafer to high temperature oxygen (low growth rate) or steam (high growth rate). Result is silicon-dioxide, 1,000s of Angstroms thick.
The edges of the integrated circuit are usually protected against ionic intrusion, with a "seal ring" where the metals and implants are tapered down to pure silicon substrate. But be careful; the seal-ring is a conductive path along the edge of the IC, thus allows interference to be transmitted along the edge of the IC.
For successful systems-on-chip, you'll need to evaluate break-the-sealring early on in your silicon prototyping, so you know the degradation of isolation, the damage to noise-floor, caused by deterministic noise being overtly conducted into the sensitive regions of the IC. If the sealring injects 2milliVolts of trash, on every clock edge, can you expect to achieve 100 nanoVolt performance? Oh, right, averaging overcomes all evils.
EDIT Delidding of some precision matched integrated circuits will alter the mechanical stresses imposed on the silicon, and the numerous transistors, resistors, capacitors thereon; changes in stresses alter the minute distortions of the silicon along crystal axes and alter the piezoelectric responses, which permanently alters underlying electric error sources in otherwise matched structures. To avoid this error, some manufacturers use enhanced features (extra transistors, extra layers of doping, etc) to add trim-while-using behaviors; in this, upon every power-up event the integrated circuit automatically runs through a calibration sequence.
As @WhatRoughBeast correctly noted in the comment, the CPU die placed on the PCB doesn't expose any fine structures, which are located on the other side of the die. There are even low-cost CPUs which are sold without the lid, like this one:
If you look closer, you'll see that the CPU survived not only dust and thermal paste, but also a few scratches and a cracked corner, which clearly means there's nothing important on this side of the die.
The key here, as WhatRoughBeast and PlasmaHH have said, is the lack of exposure of sensitive parts of the CPU die. Only the bottom plane seems to be exposed (a characteristic typical of flip-chip designs).
One could be inclined to think that if the chip is not flipped but a passivation layer is present, the chip would be protected enough. Unfortunately, that would only save the chip from particles but not from any other accidental damage happening due to the lid being hammered away, like broken wire bondings and crushed 3D structures (air bridges).
Also, a passivation layer isn't always present because it can severely impair a foundry process at high frequencies - this happens often with MMICs (monolithic microwave integrated circuits). I wouldn't rely on it if I didn't know positively that it's there.
In this case, I see far more dangers from the delidding process itself than from the chip being exposed in a non-clean environment after being delidded.
