A passivation layer is the final step, excluding the atmosphere. This layer is formed by exposing the wafer to high temperature oxygen (low growth rate) or steam (high growth rate). Result is silicon-dioxide, 1,000s of Angstroms thick.
The edges of the integrated circuit are usually protected against ionic intrusion, with a "seal ring" where the metals and implants are tapered down to pure silicon substrate. But be careful; the seal-ring is a conductive path along the edge of the IC, thus allows interference to be transmitted along the edge of the IC.
For successful systems-on-chip, you'll need to evaluate break-the-sealring early on in your silicon prototyping, so you know the degradation of isolation, the damage to noise-floor, caused by deterministic noise being overtly conducted into the sensitive regions of the IC. If the sealring injects 2milliVolts of trash, on every clock edge, can you expect to achieve 100 nanoVolt performance? Oh, right, averaging overcomes all evils.
EDIT Delidding of some precision matched integrated circuits will alter the mechanical stresses imposed on the silicon, and the numerous transistors, resistors, capacitors thereon; changes in stresses alter the minute distortions of the silicon along crystal axes and alter the piezoelectric responses, which permanently alters underlying electric error sources in otherwise matched structures. To avoid this error, some manufacturers use enhanced features (extra transistors, extra layers of doping, etc) to add trim-while-using behaviors; in this, upon every power-up event the integrated circuit automatically runs through a calibration sequence.