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I am using the ARTY 7 evaluation board from digilent which used the Artix-7 x35AT cpg324 packaging. Using one of the general purpose I/O banks i want to configure it for 1.8V configuration. (I am using this for 3-wire SPI to generate the spi clock and read the output from my ADC which are at 1.8V)

I looked through the documentation to configure this on the board and after going through all the relevant documents i am still unable to configure the I/O to LVCMOS18 standard.

Here is the table which mentions how to configure the files

enter image description here

And here is how i have configured in the XDC file

set_property IOSTANDARD LVCMOS18 [get_ports adc_conv_oc]
set_property IOSTANDARD LVCMOS18 [get_ports adc_din]
set_property IOSTANDARD LVCMOS18 [get_ports adc_sclk]

set_property PACKAGE_PIN V15 [get_ports adc_conv_oc]
set_property PACKAGE_PIN U16 [get_ports adc_din]
set_property PACKAGE_PIN T11 [get_ports adc_sclk]

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

The synthesized design has the following I/O port which indicates that the I?O's are configured for LVCMOS18 on bank 14 and VCC = 1.8V

enter image description here

The UG470 documentation mentions the following:

The 7 series FPGAs have two I/O bank types: high-range (HR I/O) banks support 3.3V,2.5V, and a few lower voltage I/O standards, and high-performance (HP I/O) banks support I/O standards of 1.8V or lower voltage. The dedicated configuration and JTAG I/O are located in bank 0. Bank 0 is a high-range bank type on all devices except for the Virtex-7 HT devices. Several of the configuration modes also rely on pins in bank 14 and/or bank 15. Bank 14 and bank 15 are HR I/O banks in the Spartan-7, Artix-7 and Kintex-7 families, but are always HP I/O banks in the Virtex-7 family. See UG475, 7 seriesFPGAs Packaging and Pinout Guide for bank information for each device. Note: The CFGBVS pin is not available on Virtex-7 HT devices. Virtex-7 HT devices support only 1.8V operation for configuration banks. The CFGBVS pin setting determines the I/O voltage support for bank 0 at all times, and for bank 14 and bank 15 during configuration. The VCCO supply for each configuration bankmust match the CFGBVS selection if used during configuration — 2.5V or 3.3V if CFGBVS is tied to VCCO_0, and 1.8V or 1.5V if CFGBVS is tied to GND.

but somehow i always get the output to be 3.3V. Any ideas on how to solve this? Does the Arty-7 evaluation board for some reason not allow me to configure the voltages to LVCMOS18?

Thanks

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The short and the long of it is: you can't.

The voltage used for I/Os on a Xilinx FPGA is controlled on a bank-by-bank basis, and is set based on the VCCO pin for the bank. For instance, if VCCO is powered at 3.3V, then all pins in the bank will use 3.3V I/O.

Setting an I/O standard that mentions a voltage does not make the FPGA use that voltage -- the FPGA does not contain voltage regulators! Instead, it informs the synthesis tools what voltage to expect for that bank, which may affect the drive and termination options used for I/Os. For more details, see the 7 Series FPGAs SelectIO Resources User Guide.

Anyways, all of the I/O banks available on the Arty have the following fixed VCCO inputs, which cannot be changed. In practical terms, this means that all of the I/Os you can access are 3.3V; you will need an external level shifter if you need to interface with a 1.8V part.

  • VCCO_0 - 3.3V
  • VCCO_14 - 3.3V
  • VCCO_15 - 3.3V
  • VCCO_16 - 3.3V
  • VCCO_34 - 1.35V (for DDR memory)
  • VCCO_35 - 3.3V
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  • \$\begingroup\$ Thanks for the answer @duskwuff . You are right about it. Digilent confirmed this too. Having at elast one of the banks supply different VCC would have made my life much easier. \$\endgroup\$ – CanisMajoris Mar 10 '17 at 16:02

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