# Sequential counter for repeating counting sequence

I'm aware of designing synchronous counter design for a counting sequence where I write the state table with present and next state and then followed by flip flop inputs (filled using the excitation table of the corresponding flip flop). But how to design if the states are repeating I'm not aware on how to proceed further and hence needed help.how to design a synchronous counter for a repeating counting sequence. I have listed an example .

• Count up normally to the number of steps you want using a regular counter and then use another circuit to convert the count value to the output you want. Or if you were doing this with real chips instead of just gates feed the output of the counter to a ROM lookup table to output the values you want. Commented Mar 10, 2017 at 17:07
• Could you please explain? Commented Mar 10, 2017 at 17:13
• I thought of FSM as well but then that would need extra inputs which is not allowed in counters. Commented Mar 10, 2017 at 17:14
• Sorry 3, You are actually counting a sequence of 8 states. So you need 3 bits... = 3 flip-flops. The values 0,1,2 and 3 are taken from the 2nd and 3rd bit of the counter. You ignore the first "bit". Commented Mar 10, 2017 at 17:15
• But then what if the counting sequence is something like 0-1-0-2-0-3? Commented Mar 10, 2017 at 17:19

You are actually counting a sequence of 8 states. So you need 3 bits... = 3 flip-flops.

The values 0,1,2 and 3 are taken from the 2nd and 3rd bit of the counter. You ignore the first "bit".

Or if you prefer, you can refer to the first stage as a clock divider "/2" for your two bit counter.

State machines can be simple or can get to be extremely complicated looping, input dependant beasts what give engineers nightmares.

In your simple examples you are actually asking for two different things.

First, to sequence through a pattern of N numbers then repeat. For that you need to count where you are in the sequence using your counter up to N. When N is reached you need logic to reset the counter.

Second you need logic to OUTPUT the appropriate value at each count.

If the latter is extremely complex or likely to change upon development and experimentation, it is usually done by feeding the count as an address into an E-Prom which is programmed to give out the right value on its data pins according to the counter value.

One of said data pins can be used to reset the counter so you can have a different N value, some can be used to feed back on itself as more address pins to switch pages.

As I say, it can get intricately complicated.

• What I was looking for is a generalised method. What if the counting sequence is 0-1-0-2-0-3? Commented Mar 10, 2017 at 17:20
• Then you would need some form of reset or pre-setting logic that sets the load condition state based on the current state. Without a micro the simplest way to do that is with an e-prom. Commented Mar 10, 2017 at 17:22
• @Fawaz, if it has the same outputs but different next state (and no distinction on inputs) then you have to treat it as a different state. So your new example has 6 states. Commented Mar 10, 2017 at 17:22
• It really depends on the sequence though. It does not need to get very complicated before you are better off using a programmable device. Commented Mar 10, 2017 at 17:24
• @Fawaz, a counter is a kind of FSM. Commented Mar 10, 2017 at 17:34

0,0 ,1,1 ,2,2 ,3,3 ,0,0...

Equivalent Binary rep: 00,00,01,01,10,10,11,11,00,00....

Sequence being repeated , we need to make then distinguish but using 1 bit additionally 000,100 , 001,101 , 010,110 , 011,111 , 000,100 ,.... Equivalent Decimal rep: 0,4,1,5,2,6,3,7,0,1.....

Having 8 states -> mod 8 counter Min flip flop required will be -> 3 .