I'm aware of designing synchronous counter design for a counting sequence where I write the state table with present and next state and then followed by flip flop inputs (filled using the excitation table of the corresponding flip flop). But how to design if the states are repeating I'm not aware on how to proceed further and hence needed help.how to design a synchronous counter for a repeating counting sequence. I have listed an example .
The answer is 3.
You are actually counting a sequence of 8 states. So you need 3 bits... = 3 flip-flops.
The values 0,1,2 and 3 are taken from the 2nd and 3rd bit of the counter. You ignore the first "bit".
Or if you prefer, you can refer to the first stage as a clock divider "/2" for your two bit counter.
State machines can be simple or can get to be extremely complicated looping, input dependant beasts what give engineers nightmares.
In your simple examples you are actually asking for two different things.
First, to sequence through a pattern of N numbers then repeat. For that you need to count where you are in the sequence using your counter up to N. When N is reached you need logic to reset the counter.
Second you need logic to OUTPUT the appropriate value at each count.
If the latter is extremely complex or likely to change upon development and experimentation, it is usually done by feeding the count as an address into an E-Prom which is programmed to give out the right value on its data pins according to the counter value.
One of said data pins can be used to reset the counter so you can have a different N value, some can be used to feed back on itself as more address pins to switch pages.
As I say, it can get intricately complicated.