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I'm looking for the FET (JFET, MOSFET and other more advanced variants like Heterojunctions) that has the lowest channel modulation or perhaps among the lowest. Now, before anybody argues if other FETs do have it, then at least JFETs also have it, as some sources will say. It's just that it's most pronounced with MOSFETs (along with other short channel effects), seeing they are scaled way down with the CMOS process.

But, as most of you know, it's not a parameter listed in datasheets. So I'm trying to resort to deriving by other parameters. Although I've ran into some problems. \$R_{OUT}\$ or \$R_{DS_{ON}}\$ is calculated as:

$$R_{OUT} = \frac{1 + λV_{DS}}{λI_{D}}$$

I believe that to more accurately derive \$λ\$ it ought to be (assuming \$λ\$ is a constant, giving a linear growth for the channel length modulation -- a simplified model):

$$R_{DS_{ON}} = \frac{1 + λV_{DS_{SAT}}}{λI_{D_{SAT}}}$$

$$λ = \frac{1}{R_{DS_{ON}}I_{D_{SAT}} - V_{DS_{SAT}}}$$

where pairs {\$V_{DS_{SAT}}\$, \$I_{D_{SAT}}\$} are any point past the beginning of saturation region where channel modulations has started to take effect.

Now, in the datasheet, typically, \$R_{DS_{ON}}\$ is listed with \$V_{GS}\$ and \$I_{D}\$ given. It's implied for the most part that all parameters are tested at some point in saturation. So, some \$V_{DS_{SAT}}\$ is \$V_{DS_{SAT}} ≥ V_{GS}\$. So we can have

$$V_{DS_{SAT}} = V_{GS} \quad (given) $$ $$I_{D_{SAT}} = I_{D_{RDSON}} \quad (given)$$

Though, of course, we are simplifying and linearizing clm, so we need a \$(V_{DS_{SAT}}\$, \$I_{D_{SAT}})\$ that is well within the clm effect and not at what probably is just the meeting point of the peak of the linear region and the start of saturation region. So that's the technical problem.

Other than the last paragraph, what other problem do you guys think there is?

EDIT:

I meant:

$$V_{DS_{SAT}} = V_{GS} \quad (given) + V_{extra}$$

So in the more ideal case that \$V_{DS_{SAT}}\$, under which everything is tested, it is well within the clm taking effect, we need the offset \$V_{extra}\$.

EDIT:

corrected the formula to \$R_{OUT}\$. My mistake.

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  • \$\begingroup\$ So what advantage does having a fet with the lowest channel length modulation give you?............ Aha equivalent to the early effect in BJTs! \$\endgroup\$
    – Andy aka
    Mar 11 '17 at 13:06
  • \$\begingroup\$ A more robust current source. \$\endgroup\$
    – Dehbop
    Mar 11 '17 at 13:10
  • \$\begingroup\$ Yeah I just figured that as per my amended comment! \$\endgroup\$
    – Andy aka
    Mar 11 '17 at 13:10
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    \$\begingroup\$ A more robust current source if you would only rely on that Rout, which would be silly. No matter how good your transistor, I (as a circuit designer) can always beat your single transistor by using feedback, cascoding and other tricks to significantly increase the output impedance. So you can try to find the holy grail by using a certain type and geometry of transistor but in the end it is the circuit topology which will help you a lot more in the end. \$\endgroup\$ Mar 11 '17 at 14:32
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    \$\begingroup\$ Right out of school, used 3 of 2n2222 with emitter-stiffening resistors (to handle Vbe mismatches), in current-source topo. Achieved 5,000,000 ohms Rout (1uA out of 5 volts change in Vout). Might have been limited by the Fairchild CurveTracer's input resistance. \$\endgroup\$ Mar 11 '17 at 15:33
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Long ago I went through a similar search for BJTs with the highest Early voltage. My finding was that higher voltage devices had a higher Early voltage. Turns out there is a fundamental reason for this that I won't go into.

Instead of using a high voltage device, I switched to a cascode design, which greatly increased the output impedance.

It is possible to stack more transistors into the cascode and increase the output impedance even more.

With FETs, a dual-gate device does the same thing as a cascode, but in one device.

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OK. You want a nice CCS.

Let's make a CCS with the following characteristics as an example:

  • 10mA
  • output voltage 10 ... 30V

Low Frequencies.

Let's pick a 2N3904 BJT, for instance. It has a RthJA of 200°C/W in TO-92. Every 10V on its Vce will make it 20°C warmer, and drop 40mV on its Vbe. If it has Re=100ohm, then output current will change by 400µA.

This means it has an output impedance of 25 kOhm, far from the megohms we want!

MOSFETs have temperature-dependent Vgsth, too, so they are not immune.

SPICE usually doesn't model this.

High Frequencies.

Here, output impedance will be determined by parasitic capacitances, and base driving impedance. Cbc will interact with the base resistor, and some current will also pass directly from collector to emitter.

Megohms at MHz doesn't exist, as any stray capacitance between the output and any other conductor around will eventually matter.

SPICE usually models this nicely.

Medium Frequencies

Between LF thermal and HF capacitive effects, the output impedance depends on Early effect (BJT) and channel length modulation (MOS).

In this example, the output impedance would look like this, seen on a bode plot with increasing frequency:

  • 25 kOhm at DC
  • at a fraction of a Hz (due to thermal time constants) it begins to rise
  • then it reaches a plateau, somewhere around 100kOhms - a few MOhms depending on transistor, resistor etc
  • then it goes down again due to capacitances

Before going on a quest for the right MOS, it is important to know if your use case will benefit from this MOS. This will only be the case if the impedance that matters to you is in this middle range of frequencies.

The low frequency part can be fixed with feedback and/or a cascode. A Cascode also works well for HF, up to a point.

For example if you need DC stability, forget it: just blowing air on your transistor will make the output current fluctuate more than Early effect / Channel Modulation. Use a TL431, or an opamp to help, or other kinds of more elaborate current sources.

I know this is not an answer to the question, but I feel it answers the real question behind the one asked here.

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  • \$\begingroup\$ I don't have much problems with temperature fluctuations. I'll just pick a bias temperature and then keep it at that in a temperature regulated enclosure. \$\endgroup\$
    – Dehbop
    Mar 11 '17 at 20:23
  • \$\begingroup\$ There are passive ways to implement a current source, well, to be more honest, a current limiter. But as for your current sources as stated above, if it works by compensating for the voltage across it by a large part (in linear, polynomial or exponential functions, etc, and it's not scaled down by a very tiny constant, like K in \$I_{D}\$ or q for electron charge), then it WILL BE subject to problems in higher frequencies. Looks like all you solution above qualify in my description (opamps, BJT with emitter resistors -- voltage modes). \$\endgroup\$
    – Dehbop
    Mar 11 '17 at 20:31
  • \$\begingroup\$ By mentioning K and q, I mean them in very loose analogy of small factors about a less than a tenth or so values. \$\endgroup\$
    – Dehbop
    Mar 11 '17 at 20:36
  • \$\begingroup\$ Can you say what impedance you need your CCS to have, and more important, what are the frequencies of interest? \$\endgroup\$
    – bobflux
    Mar 11 '17 at 20:55

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