# How does triple level cell FLASH memory achieve 3 bits per cell?

Originally each cell of FLASH memory held either a high or low level or state, and reflected one bit of information; 0 or 1.

Mutli-level FLASH was then developed, with often four levels of voltage possible for each cell. These four voltage levels were encoded and decoded to represent two bits of information; 00, 01, 10, or 11.

Now Triple-level FLASH memory can store three bits of information in one cell; 000, 001, 010, 011, 100, 101, or 111.

How does going from four levels to three levels allow the representation of three bits instead of two bits of information? What am I missing here?

Trying to read this article I think I see eight voltage levels shown in this figure. I can easily understand how that could store eight bits - but why would it then be called "triple-level" and not "octa-level"?

– uhoh
Mar 12, 2017 at 11:44
• 3 bits = 8 possible configurations = 8 levels needed. AFAIU, there is a lot of secrecy and processing in high density flash chips. So maybe some cells have only 5 or 6 levels, bits are calculated from the state of several transistors. Mar 12, 2017 at 11:54
• @TEMLIB AFAIK there is virtually zero secrecy in commercial IC chips (except for those occasional little drop-ins for espionage). Aggressive deconstruction and reverse engineering abounds. But there is certainly a lot of propriety - so even of many people know, they may not want to write about it at length here in stackexchange.
– uhoh
Mar 12, 2017 at 12:00

According to the source you linked,

Samsung announced a type of NAND flash that stores three bits of information per cell, with eight total voltage states. This is commonly referred to as Triple Level Cell (TLC)... [emphasis added]

So it stores 3 bits by using 8 voltage levels, just as you'd expect; not 3 levels as your question text claims.

As for why they called it "triple-level" and not "octa-level", probably the marketing guys just thought "triple-level" sounded better.

• So it is eight levels, and not three levels as the semiconductor industry claims. [emphasis added] :) Thank you for shedding some light upon the mystery of the three levels. I haven't gotten over the name "Tri-gate FET" (I know, there sort-of are three gates) and now there's Triple Level FLASH. Do you think this is a total mis-nomer, or could there be three levels of something? Perhaps three levels of some circuit element to decode the eight levels of voltage? I can't believe a term used so widely by stickler electrical engineers is just plain wrong.
– uhoh
Mar 12, 2017 at 16:27
• Where do you see the semiconductor industry claiming it's 3 levels? The source you linked (two links going to the same Wiki article) says 8 levels as I quoted. Mar 12, 2017 at 16:29
• cf micron.com/products/nand-flash/tlc-nand Am I making such a great leap to believe that saying "triple-something" means that there are three of the somethings?
– uhoh
Mar 12, 2017 at 16:58
• See also the second paragraph here; "... That’s not how the term is typically used, and until Samsung demonstrates that it’s built TLC NAND with MLC characteristics in both performance and longevity, it’s a misapplication of terminology for the sake of marketing." which seems to be complaining more about the use of multi than triple if I understand correctly, which I am not sure that I do.
– uhoh
Mar 12, 2017 at 17:02
• This is a marketing question, not an engineering question. Looks to me like the "triple" refers to the number of bits, not the number of levels. Sorry if you don't like it, but marketing people rarely consult engineers when they're making these choices. Mar 12, 2017 at 17:26

I've made analog floating gates with 8-bits per cell, and we actually had a few with 16-bits per cell. The weird "hump chart" that you have is how you read out. If you had a clock and differential amplifier, you check to see if you've changed state from 0 to 1 every clock, and that then tells you how many effective "bits" you have because the "lines charge" and the floating-gate is actually a programmable current source. The constraints are actually the amount of capacitance as that relates to electron storage when considering noise. You also have to be more careful with your programming. There's a quick writeup on my analog floating gates here, and if you push through the math for a specific process, you can figure out the number of bits, noise margin, etc.

• This should probably be asked as a separate question - if data is written and read as a quantity of charge as defined by a constant current and clocked time intervals rather than a gate voltage, what's the best way to think about the source of the noise? (BOth this and that answer provide very helpful information by the way!)
– uhoh
Mar 12, 2017 at 18:03
• The noise is from the Poisson transport on the difference amplifiers and other circuits. This is, unfortunately, architecture dependent. Just consider that all the floating gate is doing is storing a voltage on the gate that gives a current. You would just calculate the behavior and charge times for the lowest current and then figure out your tolerances. Mar 12, 2017 at 18:44
• Well all the floating gate is doing is storing a charge. It may manifest itself as a voltage, and that is subject both to noise and to a slow change in proportionality constant over the lifetime of the cell, but charge is the thing that is stored.
– uhoh
Mar 12, 2017 at 18:50
• @uhoh I should have said "setting a voltage" as charge is indeed stored. Mar 12, 2017 at 19:27