I'm working on a design in Xilinx Zynq. After synthesis and implementation, the worst negative slack is about 8.9ns which means that the circuit runs at about 112MHz. However after adding ILA cores in order to debug some signals, the worst neg. slack falls to 4.180ns which effectively doubles (nearly) the working frequency.
I believe that this is due to different re-arrangement of the LUTs inside the FPGA, but could someone answer me for sure? Why more logic provides faster circuit?