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I'm working on a design in Xilinx Zynq. After synthesis and implementation, the worst negative slack is about 8.9ns which means that the circuit runs at about 112MHz. However after adding ILA cores in order to debug some signals, the worst neg. slack falls to 4.180ns which effectively doubles (nearly) the working frequency.

I believe that this is due to different re-arrangement of the LUTs inside the FPGA, but could someone answer me for sure? Why more logic provides faster circuit?

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  • \$\begingroup\$ It probably means you were implementing without timing constraints so the tools simply accepted the first solution they got. How on earth can we tell without knowing your constraints? Add some and see if it meets them without ILA. \$\endgroup\$ – Brian Drummond Mar 12 '17 at 13:47
  • \$\begingroup\$ I'm implementing without constraints. I'm completely ignorant about constraints and how should I add them to my design. So the general answer is that, the tools are just accepting the first possible solution, in my case at least. \$\endgroup\$ – Arkoudinos Mar 12 '17 at 14:26
  • \$\begingroup\$ Then learning about timing constraints will answer your question. \$\endgroup\$ – Brian Drummond Mar 12 '17 at 14:28
  • \$\begingroup\$ Sometimes adding logic to reduce signal load (replicated gates) will increase frequency. \$\endgroup\$ – TEMLIB Mar 12 '17 at 15:45
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One can only guess and you probably guessed correctly.

The real question is does it matter? If you were okay with 112Mhz then it should not matter.

When I was doing chip design the simulator used the track capacitance from one corner of the die to the opposite corner to calculate worst case delay. A smaller die would have shorter delays.

My guess is when more real estate was available the maximum delay was longer. Now your logic will be routed in a smaller area so the delay times will be less.

If it matters, ask Xilinx.

There is also the possibility that the ILA introduced some relaxed time constraints. The ILA is supposed to inherit your time constraints. Maybe if you had none your timing defaults to constraints defined in the ILA.

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  • \$\begingroup\$ I'm doing some "research" work (if you can put it that way) so I want to see what is the maximum capable speed of the IP I designed. As I mentioned on another comment, I'm learning through the process so I'm trying to find out what is happening. \$\endgroup\$ – Arkoudinos Mar 12 '17 at 14:37
  • \$\begingroup\$ It is a real possibility the timing improved. If you did not change anything other than adding the ILA, the numbers should be good unless there is a bug in the simulator. Also updated my answer. \$\endgroup\$ – Misunderstood Mar 12 '17 at 14:57

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