The questions asked in the books (textbooks) are usually based on what is being said/discussed in the book. The question asked
Why can't you use microprocessor I/O pins as chip enable pins for ROM and RAM?
is broad one, requiring precise definition of the terms listed in it, at least
- what I/O pin is?
- what chip enable signal is?
I scanned online version of the book to clarify it, and unfortunately definitions are weak in relation to this question.
Page 73 has title I/O pins not giving definition of what are they (in particular which other pins exist, and what are the difference between their classes).
Same issue with chip enable, it is mentioned several times, and you know that it is there, book explains how to operate it and it is assumed that its purpose is clear basing on the description how it should be operated.
Even more confusing for this question is figure 3.19 on page 74 where pins marked I/O are used to control EEPROM. EEPROM is a subclass of ROM, thus this picture means that you actually can use I/O pins to control ROM (again, I did not find chip enable term properly defined).
Ok, now to the right answer to this question - according the book. You will find it on the page 68 which says that
PAL will drive the chip enable signals
I can not see whole the book online, but I guess that this statement is based on the premise that CE is usually complex function of address and other control signals, these signals are fed into PAL (glue logic) which has single chip enable output signal for specific device in the circuit.
Other considerations relating to the question asked:
- What I/O pins are - Z80's address pins are output pins, not I/O pins. Data pins are I/O pins. There're no other bidirectional pins in Z80;
- Bus cycle and synchronous operation - it is probably bad idea to trigger start of ROM/RAM access cycle with multiple signals (e.g. use address lines) as it may not be physically possible, and there should be some logic in between creating single strobe signal informing device about its activation. While it is possible to control devices with non-buffered inputs (asynchronous devices), synchronous devices will need clock and chip enable (device activator) signals as inputs to start operation;
- it is very bad idea to have chip enable input signal being driven by another input signal - when I/O pin is in input mode. These situations will cause conflicts on the bus, over-current and physical damage of the chips (because several chips may think they are selected and start outputting data onto the bus). Thus chip enable should by default be curcuit's output pin towards ROM/RAM's input CE wire.