Why can't you use microprocessor I/O pins as chip enable pins for ROM and RAM?

Question

I have been reading a textbook on Embedded systems called An Embedded software primer by David E Simon (great book btw). I am trying to answer questions after each chapter, I got through first 2 chapters, in chapter 3 there is a question

Why can't you use microprocessor I/O pins as chip enable pins for ROM and RAM?

You normally Encode Address pins to do this.
Which also got me thinking, can you use Data pins and address pins as I/O pins for a processor (Like I/O pins you can write certain bits of data pins HIGH), if not what is the difference between them, do I/O pins have more current driving capability?

Answer 1

You can as long as you only want to access one memory type at a time.

Typically a micro is pulling in instructions from ROM in one or two cycles and the data from RAM in the next few cycles. Wash and repeat. IO lines will not respond fast enough so you decode the top few address lines to do this.

You can use the IO lines to select banks of memory. For instance if you had a lot of data stored in RAM or ROM chips you could split this into banks and use the IO lines to select between banks.

Answer 2

ROM and RAM chips have exactly as many address lines as they need, so any pattern will form a valid address, so the IC always responds on the bus.

Obviously that is not what you want, because you only want one reply, so you generate the chip enable signal in a gate logic that compares the address range (i.e. the address lines not going to the memory chip).

On the C64, some GPIOs also go into this gate logic to allow switching certain areas between ROM and RAM. The write enable line is also used in that logic, so writes always address the RAM, which allows copying the ROM contents for later manipulation easily.

The same thing was done on PCs with the BIOS memory: at startup, the BIOS EEPROM would be mapped, then the BIOS code would copy the contents to RAM at the same address, then disable the EEPROM (because it is slower than regular RAM).

Answer 3

The questions asked in the books (textbooks) are usually based on what is being said/discussed in the book. The question asked

Why can't you use microprocessor I/O pins as chip enable pins for ROM and RAM?

is broad one, requiring precise definition of the terms listed in it, at least

• what I/O pin is?
• what chip enable signal is?

I scanned online version of the book to clarify it, and unfortunately definitions are weak in relation to this question.

Page 73 has title I/O pins not giving definition of what are they (in particular which other pins exist, and what are the difference between their classes).

Same issue with chip enable, it is mentioned several times, and you know that it is there, book explains how to operate it and it is assumed that its purpose is clear basing on the description how it should be operated.

Even more confusing for this question is figure 3.19 on page 74 where pins marked I/O are used to control EEPROM. EEPROM is a subclass of ROM, thus this picture means that you actually can use I/O pins to control ROM (again, I did not find chip enable term properly defined).

Ok, now to the right answer to this question - according the book. You will find it on the page 68 which says that

PAL will drive the chip enable signals

I can not see whole the book online, but I guess that this statement is based on the premise that CE is usually complex function of address and other control signals, these signals are fed into PAL (glue logic) which has single chip enable output signal for specific device in the circuit.

Other considerations relating to the question asked:

• What I/O pins are - Z80's address pins are output pins, not I/O pins. Data pins are I/O pins. There're no other bidirectional pins in Z80;
• Bus cycle and synchronous operation - it is probably bad idea to trigger start of ROM/RAM access cycle with multiple signals (e.g. use address lines) as it may not be physically possible, and there should be some logic in between creating single strobe signal informing device about its activation. While it is possible to control devices with non-buffered inputs (asynchronous devices), synchronous devices will need clock and chip enable (device activator) signals as inputs to start operation;
• it is very bad idea to have chip enable input signal being driven by another input signal - when I/O pin is in input mode. These situations will cause conflicts on the bus, over-current and physical damage of the chips (because several chips may think they are selected and start outputting data onto the bus). Thus chip enable should by default be curcuit's output pin towards ROM/RAM's input CE wire.