# FPGA proper SDC constraint for hsync pulse

I have a design where video data comes in over the altera altlvds_rx lvds receiver. One of the parallel bits that comes out the other side represents H-Sync which will show up for a few clock cycles every horizontal video line. One always block in the design uses h-sync to count them so something like always @(posedge hsync)...

Now Quartus tells me it has decided hsync is a clock which I kind of get and then it tells me it is unconstrained. What kind of constraint would I put here? Do I declare it a clock and make it have a very unbalanced duty cycle? Hsync period is quite large compared to the video clock but the positive portion of the pulse is only a few video clocks wide.

• You shouldn't use HSync as a clock. You should use the pixel/video clock, and then HSync as an enable signal. Mar 14 '17 at 18:55
• Don't route these signals to the clock inputs of flip-flops. Recommend you look up 'synchronous logic design' on the Internet, should lead you to some well-written guidance. Mar 14 '17 at 21:39

Synchronize and edge detect the hsync input with something like this:

reg hsync_reg = 0;
reg hsync_delay_reg = 0;
wire hsync_posedge = hsync_reg & ~hsync_delay_reg;

always @(posedge clk) begin
hsync_reg <= hsync;
hsync_delay_reg <= hsync_reg;
end


Then count the pulses of hsync_posedge with something like this:

reg [7:0] count_reg = 0;

always @(posedge clk) begin
if (rst) begin
count_reg <= 0;
end else if (hsync_posedge) begin
count_reg <= count_reg + 1;
end
end


In this case, everything is timed by clock and you don't need any special timing constraints. This is also known as using hsync_posedge as a clock enable, since it's roughly equivalent to routing the signal to the 'enable' input on a flip flop.