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I am trying to simulate gate charge profile and switching loss curves of transistor as in the circuit below. I used ideal current source (30uA) for load, clamp diode (piecewise-linear model with ron = 1mΩ and Vth = 5mV as shown in the picture below).

There is a strange period I don't understand, when VG < Vth, ideally the transistor current should be zero and all ideal current source (30uA) should flow through the diode. However, as you see in the picture below, the diode current is very large (more than 500uA) here. I can not explain what is happening here. Could anyone explain this?

Here is the diode model (I got this from Cadence community forum). The diode symbol is from analogLib libray.

subckt idealDiode (a c)
// note, the on resistance shouldn't be below 1mOhm
D1 (a c a c) relay rclosed=1m vt1=0.0 vt2=5m
ends idealDiode

enter image description here

enter image description here enter image description here enter image description here

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  • \$\begingroup\$ 657 pA isn't large. \$\endgroup\$ – Andy aka Mar 14 '17 at 19:38
  • \$\begingroup\$ @Andyaka: it is more than 500uA not pA. \$\endgroup\$ – anhnha Mar 14 '17 at 19:55
  • \$\begingroup\$ Perhaps your ideal diode model includes some parasitic capacitance? Can you track down the model definition and include that in your question? \$\endgroup\$ – user49628 Mar 14 '17 at 20:11
  • \$\begingroup\$ I have just added the model. \$\endgroup\$ – anhnha Mar 14 '17 at 20:40
  • \$\begingroup\$ This does look like pretty unusual behavior to me. A few suggestions for debug: as a sanity check, plot all the terminal currents of the FET. Also, try the experiment with a resitive load between the supply and the drain of the FET, instead of the current source and diode. \$\endgroup\$ – user49628 Mar 14 '17 at 20:58
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I suspect the current spike is caused by parasitic capacitances inside the FET. Consider the simplified circuit below:-

schematic

simulate this circuit – Schematic created using CircuitLab

C1/R1 and C2/R2 are the FET's Gate-Source and Gate-Drain capacitance and series resistance. I don't model the rest of the FET because we are only interested in the period before it turns on.

When Vin is 0V, C2 charges to 1.805V and then draws no current, so D1 just consumes the 30uA coming from the current generator.

When Vin transitions to 1.8V, voltage on the Drain side of C2 also rises by 1.8V. It then discharges through R2 into D1, causing a current spike that is positive relative to the diode and negative relative to the Drain.

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