I am trying to simulate gate charge profile and switching loss curves of transistor as in the circuit below. I used ideal current source (30uA) for load, clamp diode (piecewise-linear model with ron = 1mΩ and Vth = 5mV as shown in the picture below).
There is a strange period I don't understand, when VG < Vth, ideally the transistor current should be zero and all ideal current source (30uA) should flow through the diode. However, as you see in the picture below, the diode current is very large (more than 500uA) here. I can not explain what is happening here. Could anyone explain this?
Here is the diode model (I got this from Cadence community forum). The diode symbol is from analogLib libray.
subckt idealDiode (a c)
// note, the on resistance shouldn't be below 1mOhm
D1 (a c a c) relay rclosed=1m vt1=0.0 vt2=5m