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I am working on a assignment do make a demux with 2^n outputs with n select lines. I have a my input (x bit wide, in this case x is 32bits) and my enable pins taken care of. But I don't know how to go about setting up entity so that my output is 2^n with n select lines. So far my entity declaration looks like:

-- Entity declaration
entity DEMUX is
-- Get the size of an integer
generic(Len :integer);
-- Map input, output, selection and enable signal ports
port(
   Inp : in std_logic_vector(Len-1 downto 0); -- Input pin
   Ena : in std_logic; -- Enable pin
   Sel : --How to set select lines?
   Oup : --How to set outputs?
);
end MUX; 
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  • 1
    \$\begingroup\$ Duplicate of stackoverflow.com/questions/42795450/… \$\endgroup\$ – Brian Drummond Mar 14 '17 at 23:32
  • \$\begingroup\$ I didn't know we were not allowed to duplicate questions across sites. I'll remove the other one because I feel like it would be more relevant here. \$\endgroup\$ – dikshant Mar 14 '17 at 23:37
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What function you want to give to Sel signal?

If this is a top level module you can use package and calculate your constants there as following:

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;

package dmux_const_pkg is
    constant IWIDTH : integer:= 3; -- for example
    constant SWIDTH ; integer:= 0;
    constant OWIDTH : integer:= 2**IWIDTH; -- 2^3
end package_name;

and include it to your top module as: use work.dmux_const_pkg.all; and in module declaration you can use the constants:

entity DEMUX is
-- Map input, output, selection and enable signal ports
port(
   Inp : in std_logic_vector(IWIDTH-1 downto 0); -- Input pin
   Ena : in std_logic; -- Enable pin
   Sel : in std_logic_vector(SWIDTH-1 dwonto 0);--How to set select lines?
   Oup : out std_logic_vector(OWIDTH-1 downto 0)--How to set outputs?
);
end MUX;

If this is not a top module you can declare all widths in generic and calculate it in up-to-this module:

entity DEMUX is
-- Get the size of an integer
generic(
    IWIDTH : integer;
    SWIDTH : integer;
    OWIDTH : integer
);
-- Map input, output, selection and enable signal ports
port(
   Inp : in std_logic_vector(IWIDTH-1 downto 0); -- Input pin
   Ena : in std_logic; -- Enable pin
   Sel : in std_logic_vector(SWIDTH-1 dwonto 0);--How to set select lines?
   Oup : out std_logic_vector(OWIDTH-1 downto 0)--How to set outputs?
);
end MUX;

Top-level module:

entity top_level_module(
...);
end top_level_module;
architecture arch of top_level_module is

constant DMUX_IWIDTH : integer := 1;
constant DMUX_SWIDTH : integer := 0;
constant DMUX_OWIDTH : integer := 2**DMUX_IWIDTH; 

component DEMUX is
generic(
    IWIDTH : integer;
    SWIDTH : integer;
    OWIDTH : integer
);
-- Map input, output, selection and enable signal ports
port(
   Inp : in std_logic_vector(IWIDTH-1 downto 0); -- Input pin
   Ena : in std_logic; -- Enable pin
   Sel : in std_logic_vector(SWIDTH-1 dwonto 0);--How to set select lines?
   Oup : out std_logic_vector(OWIDTH-1 downto 0)--How to set outputs?
);
end component DEMUX;

begin
    DMUX: DEMUX
    generic map(
        IWIDTH => DMUX_IWIDTH, 
        SWIDTH => DMUX_SWIDTH, 
        OWIDTH => DMUX_OWIDTH
    ) port map (
        ...
    );
...
end arch;
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  • \$\begingroup\$ Could you explain what a top level module exactly is in VHDL? I am new to the language. \$\endgroup\$ – dikshant Mar 15 '17 at 2:40
  • \$\begingroup\$ @dikshant Top module is the highest module in hierarchy. For example, if you want to design just DEMUX, so DEMUX will be the top module, but if you want to design complex system which will be use DEMUX as part of it, so you will have top module with DEMUX included in. Now is it clear for you? Also I reread initial question and want to add to my answer, if you want make a demux with 2^n outputs with n select lines, your input should be one bit. But if you have bus as input you should explain a function of Sel \$\endgroup\$ – Roman Mar 15 '17 at 2:49
  • \$\begingroup\$ So my instructions state to simply make a demux so for now I guess it is the top level module. Since it's for an assignment the question states, "design a x-bit, 1-to-2^n de-multiplexer, x and y being two parameters." So I interpreted that as a x bit wide input with 2^n outputs. Is there any particular reason why my input has to be 1 bit if I want 2^outputs? \$\endgroup\$ – dikshant Mar 15 '17 at 3:39
  • \$\begingroup\$ @dikshant you can read the link there has a good explanation how demux works. In case when you have bus (X width) as input you will have more then 2^n width output. Exactly, you will have X*2^n output, because you address all bus (X width) to one of output (2^n variation). But if you want to have 2^n output width, which bit of input bus (X width) do you want to take? \$\endgroup\$ – Roman Mar 15 '17 at 4:00

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