I was testing the TI TXB0108 today to shift 3.3V from a MCU to a DSP. The DSP connector only has 17 digital inputs, and a ground (no VCC), and expects 0-5V. The 3.3 and 5V power are both being supplied on the MCU side. I first tested the output with a scope, and got nice clean transitions. However, once I added a cable (twisted pair ribbon, but only 18" long), the first 50-100 us of the rise was a mess, and then it quickly reached 5V, with a relatively quick fall.

I'm curious what I could do differently. This application does not require a timing signal, only 16 bits and a strobe bit (to latch the input). The strobe will only fire at most 10 times per second (pulse of any length > 250 us) but there needs to be sub-millisecond delay. And as far as I can tell, the DSP input is buffered, so there should be much of any current draw (but I haven't verified this yet). Also, although the logic level translator is bidirectional, the signal will only -ever- go from the MCU to the DSP.


Of course (sadly), I can't reproduce the problem today. I get -exactly- the same scope trace with the following:

  • scope tied directly to level translator
  • scope connected through 18" of twisted ribbon to level translator
  • scope connected through 18" of twisted ribbon to 100 Ohm resistors to level translator
  • scope connected through 18" of twisted ribbon to buffer to level translator

I didn't have enough resistors to try more than 1 bit and the strobe, so I wasn't able to test more. However, I did occasionally get flaky results with the ribbon tied directly to the level translator, so I added the buffer (which has 6 channels), so I could get at least 5 bits - and it was rock solid.

Image: Y1 is strobe, Y2 is bit0. The strobe is delayed by 50us.

enter image description here

  • 1
    \$\begingroup\$ Can you share oscilloscope snapshots? \$\endgroup\$ – User323693 Mar 15 '17 at 2:16
  • \$\begingroup\$ Probably tomorrow, yes. \$\endgroup\$ – Adam Jones Mar 15 '17 at 2:23

The TXB has automatic direction sensing, which implies that its I/O pins do not behave like those of normal CMOS devices. TI's TXB application report says:

We call the TXB-type translator "weak-buffered", because it is strong enough to hold the output port high or low during a dc state, but weak in that the 4-kΩ impedance buffer can be easily over-driven by a system driver connected to the A or B port when a bus direction change is desired.

The TXB is designed to connect CMOS devices on the same board. If the (capacitive) load on its outputs is too high, the edge-rate accelerators do not longer work.

If you do not actually need automatic direction sensing, use some other level translator that is unidirectional or has a separate direction control input. (Translation between 3.3 V and 5 V can also be done with simple buffers with TTL-compatible or 5V-tolerant inputs.) Those devices have enough drive strength for longer cables, and their signals can be terminated in the usual ways.

  • \$\begingroup\$ I stumbled upon cmos-ttl compatible line drivers, and I'm going to try them. \$\endgroup\$ – Adam Jones Mar 17 '17 at 12:01

Install 100_ohm series resistors at the transmit side. On one of the digital signals. And verify this termination: series-at-source produces a clean rising and falling edge at the destination.

With only one ground-wire between TX and RX, you need to either WAIT for signals to settle to high or to low, before strobing/latching, or add some more GND wires, scotchtaped to the gray ribbon cable and soldered to GND at both ends.

And you probably meant 100 nanoseconds, right? If the sloppy behavior is 100uS, you need a VDD bypass cap at the level-translator IC.

  • \$\begingroup\$ No, I'm pretty sure it was in the microseconds range. I'm currently delaying the strobe by 50 us, and the sloppy rise was on the same order (as best as I can remember - I'll provide shots tomorrow) \$\endgroup\$ – Adam Jones Mar 15 '17 at 2:24
  • \$\begingroup\$ Just out of curiosity, would a buffer also be appropriate? Not that I don't want to get away with passive components, I'm just curious if the bi-directional translator can provide enough current and/or is getting confused by the ringing. \$\endgroup\$ – Adam Jones Mar 15 '17 at 2:36
  • \$\begingroup\$ Normal edges from TTL or CMOS, between chips, are 1nanosecond; controlled-slew-rate signals, used to reduce radiated EMI to pass FCC requirements, can be quite slow; to see 100 microsecond edges, I wonder if the VDD is broken, or the GND is broken. \$\endgroup\$ – analogsystemsrf Mar 19 '17 at 11:18

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