I am currently working on interacting with SSD memory through a FPGA using SATA protocol. I am using a Xilinx KC705 evaluation board and SSD is from Samsung. I have connected the SSD device to the KC705 board through a FMC connector. I have used Xilinx 7 Series GTX for the PHY layer. I am trying to work on the initialization part of the SATA protocol and that's where I am facing issues.

I have been able to do the OOB initialization with the SSD device. After that I have been able to negotiate the speed between host(FPGA) and device(SSD) at SATA II based on recognition of ALIGNp at the line rate specified. I am stuck at the "IDLE" state of the link layer state machine.

As per the SATA spec, the device link layer transmits SYNCp continuously to the host in IDLE state. What I am getting is that, I receive SYNCp for some period then I stop receiving as shown in Figure 1. Afterwards, I receive ALIGNp and SYNCp in random numbers as shown in Figure 2. I have captured the waveforms on chipscope.

Figure 1

Figure 2

Description of the signals captured on Chipscope :-

"currPrimitive" - The primitive that host link layer is sending presently.

"currState" - State of my state machine (not relevant)

"rxelecidle" - A value '0' denotes that the OOb initialization has been completed and the device is sending primitives.

"prim_align_det" - ALIGNp primitives obtained from device.

"prim_syn_det" - Syncp primitives obtained from device

Observations :- As it can be seen in figure 1, I receive ALIGNp from device and after receiveing 100 ALIGNp, my link layer starts sending SYNCp. The device then starts sending SYNCp but after few numbers it stops and then in figure 2 you can see that the ALIGNp and SYNCp are received randomly, This behavior is confusing.

Hence my question is what could be the possible reasons for such behavior of the device. Here are few of my ideas :-

1) "Maybe the device lost synchronization with the host" - But how is this possible. After I receive around 100 ALIGNp(I have chosen to count upto 100 ALIGNp continuously for deciding on that the rx data is aligned), Host link layer sends ALIGNp untill it recognizes 100 SYNCp continuously from device. So I am assuming that My host is sending enough ALIGNp for the device PHY layer to synchronize (because the device itself is sending SYNCp at the hand-shaken line rate).

2) As per the SATA spec, after every 256 Dwords, two ALignp need to be send. I have a section of code that does the job. It counts and sends 2 ALIGNp. That is for every 256 Dwords, 254 are non-ALIGNp and 2 are ALIGNp. This is done while my link layer is in state "9" i.e. sending SYNCp. So, this should also not be an issue(maybe, not sure).

3) I have checked that the reference clock to my GTX is stable and similar to what I selected during IPcore generation.

I can't think of any other issues which might cause such behavior. Please share your views on what might be the possibilities. Also you can share your own experiences of SATA device behavior in it's idle state.


1 Answer 1


Ok, so I have been able to figure out the reason behind this behavior where the host link layer stops receiving SYNCp after certain time.

The reason is the use of CONTp by the device. After sending SYNCp for certain number of times, the device sends CONTp to imply that the SYNCp is being repeatedly sent by the device. Hence, even though the device link layer is in it's IDLE state and is supposed to send SYNCp continuously, it chooses to stop sending SYNCp after sending a CONTp, which does the same job of repetitive sending of SYNCp.

For more details, Section "9.4.5 CONTp Primitive" of the "Serial ATA Revision 3.0" spec can be referred.


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