As mentioned, combinatoric logic with feedback is used to implement flip flops and latches, so it isn't intrinsically bad.
However, there are some specific problems when using it, especially in an FPGA (where you are presumably eventually going to drive flip flips). The first problem is that the settling time of a circuit with feedback is not statically determinable. In the absence of feedback, the synthesis tool can simply sum the propagation delays of all the gates to determine if the outputs will settle by the next clock cycle, and thus determine the maximum operating frequency of a circuit. If there is feedback, that is not possible.
Second, the type of feedback you are describing normally generates latches, not flip-flops. This presents a few problems. A latch can 'see' temporary / intermediate states and respond to them in a way that you don't expect. For instance, if you have a counter that goes through the states
11, and you want a latch to fire when you see the state
11. During the transition between
10 you may go through the state
11. Then, if you recompile the supply voltage changes, or the chip temperature changes the behavior can shift so instead you go through an intermediate state. This instance could be fixed by using Gray codes, but that won't always be possible.