I am trying to implement a VHDL circuit similar to the one in this image:
This Simulink simulation works as expected, but trying to implement the same in VHDL is another issue. The problem is that Matlab/Simulink produces an output of the filter immediately, whereas this particular filter takes 43 clock cycles in VHDL to produce a valid output. This causes the feedback path to be "late" compared to Simulink, and delaying the signal generator input to match this delay will only further delay the corresponding filter output.
There must be some way to account for this real world delay that I'm not seeing. Any tips?