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I am trying to implement a VHDL circuit similar to the one in this image:

circuit

This Simulink simulation works as expected, but trying to implement the same in VHDL is another issue. The problem is that Matlab/Simulink produces an output of the filter immediately, whereas this particular filter takes 43 clock cycles in VHDL to produce a valid output. This causes the feedback path to be "late" compared to Simulink, and delaying the signal generator input to match this delay will only further delay the corresponding filter output.

There must be some way to account for this real world delay that I'm not seeing. Any tips?

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  • \$\begingroup\$ Don't know VHDL, but is it possible you need to have valid data (zeroes) in your delay line when you start? \$\endgroup\$ – JRE Mar 16 '17 at 17:51
  • \$\begingroup\$ Well maybe you need a parallel implementation of the FIR filter that will output data after one clock cycle. I have not done such a thing myself but I think it is possible. \$\endgroup\$ – Claudio Avi Chami Mar 16 '17 at 17:56
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    \$\begingroup\$ Perhaps you should show your VHDL to help us help you. \$\endgroup\$ – user2233709 Mar 16 '17 at 18:02
  • \$\begingroup\$ This is an old question, but I am confused what you mean by it takes 43 clock cycles to produce a valid output? Does that mean that data takes 43 clock cycles until it is what you expect? \$\endgroup\$ – Addison Feb 25 '18 at 3:38
  • \$\begingroup\$ Yes. There are 43 clock cycles between an input sample and the corresponding filtered output. \$\endgroup\$ – user3691539 Feb 27 '18 at 13:30
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There are fundamentally two approaches to FIR in an FPGA and they trade area for speed (This is the general tradeoff in an fpga).

You can build a FIR as a mess of registers (1/z), multipliers and adders that will produce a result in one clock cycle, the cycle may be fairly slow because of the adder tree and the area will be large because of the DSP block and adder chain usage but it will work. For higher performance you can pipeline the adder tree, still one result per clock but now with latency, but you can clock it faster.

The other (and far more common approach) is to have a clock running at a significant multiple of your sample rate, then one ram (Historical data), one rom (coefficients) a few counters, a single multiply/acc core and a state machine gets you a result in one sample clock, but it takes approximately one high speed clock cycle per tap.

There are obviously hybrid approaches that trade speed and area, but those are the common ways you see this done.

Obviously, very long filters can favor fourier based approaches, but that is a whole other can of worms.

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FIR filters do not have feedback.

When you design a IIR filter the output is fed back to the input.

You can clearly see that if you put a unit pulse into your circuit, it will take a very long time to ring down. That means that it is a IIR filter.

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    \$\begingroup\$ I think you didn't understand the question. The OP didn't say that the FIR has a feedback, he only wants to build a system based on a FIR. And the system is the one with a feedback, not the FIR \$\endgroup\$ – Claudio Avi Chami Mar 16 '17 at 20:03
  • \$\begingroup\$ @ClaudioAviChami Then the title of the question needs to be changed? \$\endgroup\$ – skvery Mar 16 '17 at 20:12
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    \$\begingroup\$ No because it is the circuit the one who has the feedback, not the filter. Are you answering based on the title? \$\endgroup\$ – Claudio Avi Chami Mar 16 '17 at 20:22
  • \$\begingroup\$ I see what you are saying. My title was poorly worded. \$\endgroup\$ – user3691539 Mar 17 '17 at 12:51

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