This is a followup to my previous question.

The code I was using, pin assigmnets and the theoretical timings for VSYNC and HSYNCH were correct.

I have used to oscilloscope to look at the signals, and have gotten very weird results that I am unable to explain or fix.

The signals generated when displayed on one of the GPIO pins and shown on the scope have the correct duty cycle, frequency and amplitude.

If if i send the same signals to the VGA outputs and measure the voltage at the actual pins of the VGA I get very differnt results.

VSYNC displays exactly the same as it does on the GPIO, while HSYNC has a pulse which is around 0.33V and its frequency and duty cycle matches the one of the VSYNC.

I think this is very interesting as VSYNC is derived from HSYNC yet VSYNC is correct while HSYNC is distorted.

I am beginning to think that the FPGA board is faulty, rather than this being some fault due to my design as I didn't even know you can unintentionally drive a signal at 0.33V.

My query is, has anyone had a similiar problem or knows how it may be possible to fix it from quartus window or should i just dump the board.


  • \$\begingroup\$ Drive strength issue? \$\endgroup\$ – pjc50 Mar 17 '17 at 9:17
  • \$\begingroup\$ In pin planner I tried both 3.3V and 2.5V. Each time the signal about 10 times smaller \$\endgroup\$ – mega_creamery Mar 17 '17 at 10:27
  • \$\begingroup\$ If it's correct when measured at the pin but degrades futher downstream, that implies problems in the downstream circuit or cable. \$\endgroup\$ – pjc50 Mar 17 '17 at 11:06

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