My FPGA has an internal clock of 66.66 Mhz. An input is a video signal clocked at the same frequency.

It seems that I can't clock a process processing the data with the internal clock, as I don't know about the phase of the signal, and the two frequencies may not be exactly the same.

I know that I can use a DPRAM to clock the video signal at the internal clock. I have also read that I can use two D latches to synchronise the two clock, but I don't get how it works.

I can't use the external clock because it can't be sure it will always be on.

Then, how can I process external data?

  • 3
    \$\begingroup\$ There's a very good paper on the subject in general by Clifford E. Cummings titled Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs. Search for it over internet (I have a copy of it, but having difficulties finding it online). \$\endgroup\$
    – Anonymous
    Mar 17, 2017 at 14:45
  • \$\begingroup\$ Ah, here they are, scroll down to access it sunburst-design.com/papers \$\endgroup\$
    – Anonymous
    Mar 17, 2017 at 14:48

1 Answer 1


Look into clock domain crossing. There is a large body of knowledge on this subject. That said, on an FPGA you usually have 2 options:

  • Dual port fifo synchronization
  • 2 Stage register synchronization ( as you mentioned)
  • \$\begingroup\$ On a bus, you typically apply the synchroniser to the control signals, which are guaranteed to have appropriate timing wrt the data (e.g. cannot happen before ALL data bits are stable). \$\endgroup\$
    – user16324
    Mar 17, 2017 at 15:23
  • \$\begingroup\$ What if the external 66.66 MHz clock is slightly faster than the internal one? \$\endgroup\$
    – scary_jeff
    Mar 20, 2017 at 13:43

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