I have gotten very confused on the fundamentals of computer memory in regards to memory cells and chips. I have been reading Assembly Language Step By Step Programming with Linux by Jeff Duntemann and in Chapter 3 "Lifting the Hood" he dives into what a computer is, starting with how memory in a computer works (RAM, memeory chips, and cells). The confusion starts when he uses memory chip and memory cell interchangeably.

It states that transistors act as switches and have either a state of on or off which represent 1 or 0 respectively in binary. Then it states

...the transistor switch and its support components are called a memory cell.

A single computer memory cell, such as the transistor-based one we’re speaking of here, holds one binary digit, either a 1 or a 0.

So from the above quotes I have the impression that a cell holds one bit and has a transistor.

The confusion starts here:

Whereas in the beginning one chip held one transistor, in time semiconductor designers crisscrossed the chip into four equal areas and made each area an independent transistor.

Not it is stating a chip is holding the transistor but before it said the cell held a transistor. It also says the chip was redesigned to hold four transistors so in essence now a memory cell/chip holds four bits of memory not one as it said previously.

Then it goes back to using them as separate objects.

...256 memory cells could occupy one chip of silicon, usually in an array of 8 cells by 32.

Now it says chips hold cells.

The question I have is what are the differences between the cell and chip? Also if you could help clarify my confusion of how memory works.

Follow up question is how does this relate to RAM? Does RAM hold multiple chips or is the chip actually RAM in this context?

  • \$\begingroup\$ ME thinks "Whereas in the beginning one chip held one transistor, in time semiconductor designers crisscrossed the chip into four equal areas and made each area an independent transistor." is a typo... probably by the transcription typist who had a rather confused look on her/his face. \$\endgroup\$
    – Trevor_G
    Mar 17, 2017 at 17:54
  • 1
    \$\begingroup\$ As a side not, I'd also say the author of the book knows just enough to be dangerous. \$\endgroup\$
    – Trevor_G
    Mar 17, 2017 at 18:04
  • 1
    \$\begingroup\$ "Chip" is a slightly slang term for Integrated Circuit. \$\endgroup\$ Mar 17, 2017 at 20:00

5 Answers 5


Old school: A memory cell holds one bit of information, a 1 or 0. A bit and a cell can be used interchangeably. Memory chips are made up of one or more cells. In modern hardware, memory chips contain millions or billions of cells.

Modern terminology: 8-bit per cell memory?

RAM, or Random Access Memory, is a type of memory that allows random access. RAM can be made up of one or more memory chips. Here's an example of some RAM:

enter image description here


Back in the day you could see each memory "cell", made of a magnetic core, holding one bit of data. Cost about $1 per bit.

enter image description here

They put them on plug in cards.

enter image description here

Then in more modern times they put them in "chips". Cost about $0.01 per bit.

enter image description here

Then in 1972 the Intel 1103 DRAM chip was release. Cost, $0.01 per bit.

Intel 1103 DRAM chip

And you could no longer see the memory cells.

  • \$\begingroup\$ A down vote? That's ageism. This is the way I remember it. See my profile pic, that's how old I was when magnetic cores were being used. That was 50-60 years ago. I was there. Dadgum kids these days got no respect. No respect I say. \$\endgroup\$ Mar 18, 2017 at 3:56
  • \$\begingroup\$ LOL M, I remember them too, we still used them at Sperry for the military about 25 years ago. \$\endgroup\$
    – Trevor_G
    Mar 18, 2017 at 7:15

I would not rely too much on a book about software to describe how hardware works.

The RAM memory in a modern computer or computing platform can be either DRAM or SRAM. Both memory types loose their data when power goes off.

A DRAM cell is actually a small capacitor with its own transistor, it can store 1 bit. The transistor is needed to read out that bit. The data is lost when it is read and also it leaks away over time. So DRAM needs to be refreshed every few thousandths seconds or so.

An SRAM cell consists of 6 transistors as far as I know. 4 are needed to remember the data (again one bit) and 2 extra for read and write operations.

Chips always contain many cells of memory in a matrix like structure.

I think you should ignore the text:

Whereas in the beginning one chip held one transistor, in time semiconductor designers crisscrossed the chip into four equal areas and made each area an independent transistor.

as I think it makes no sense at all.

And concerning:

...256 memory cells could occupy one chip of silicon, usually in an array of 8 cells by 32.

almost any configuration is possible so he's basically saying "chips contain arrays (matrices) of memory cells."


Memory chips contain memory cells.

Each memory cell can hold a single bit of data.

Each memory cell may be made of one or more transistors.

The number of memory cells = The number of bits the memory can store.

The transistor per cell count determines the type of memory (SRAM, DRAM, flip-flop based etc).

If you're talking about SRAM based memory, each cell contains 4 transistors. Thus, a 128 byte (or 1024-bit) SRAM contains 128*8=1024 cells which turns out of be 4096 transistors. DRAM memory on the other hand is essentially 1 transistor = 1 cell, thus, a 128 byte DRAM would contain 1024 transistors.

Here's a representation of a single SRAM memory cell... A D Latch

Here's the waveform of the latch in action... Latch Waveform

When Enable i.e., E=1, Q tracks the D pin and when E = 0, Q retains its value despite D changing. Note that Q' is the logical opposite of Q.

Put together N latches and you have N-bit memory. If you tie all the N enables together as a single pin, you have an N-bit wide memory bank. If you construct another N-bit bank in a similar fashion, then overall you get 2 enable pins (Call them E[1] and E[0]), each pin controlling one set of latches (or bank) and thus you now have N-bit wide and 2 locations deep memory (Totally N*2 bits organized as N-bit x 2). The final E pin can be seen as a 1-hot address (E[1]=0 E[0]=1 selects bank 0 ; E[1]=1 E[0]=0 selects bank 1). Note that each bank can store N-bit.

To confuse matters a little, some people consider each bank to be a cell so in that case, the memory you constructed has 2 cells, each cell capable of storing N-bit. However, from the perspective of a integrated circuit design engineer, each memory cell is treated as 1-bit (and that should be the way to describe it).

Here is the logic gate level implementation (5 gates) of a latch. Note that a logic gate is built using transistors. Latch Gate Level

The chip is actually RAM. Of course, you could string together several RAM chips on a circuit board and create even more RAM (or you could just buy bigger RAM chips).


In DRAM, memory is a capacitor. Each bit, each cell, is a capacitor. The presence of many electrons in a cell defines the 1/0 value. These capacitors are built on the silicon in rectangular grids. Thus a memory chip is covered with rectangular patterns.

To read out, or to write to, just one bit at a time, requires too much circuitry.

Thus entire rows of capacitors are read out at a time, the value 1/0 of electron charge in each capacitor is stored in a group of FlopFlops/latches, and a multiplexor selects just the ONE BIT you wished. A portion of the address is used to specify the row, and rest of address tells the multiplexor exactly which BIT you wish.

To write, part of the address is used to select the Row, that entire Row is read into the FF/latches, and a multiplexor changes JUST THE ONE BIT you planned to write. Then, that entire Row of data is copied from the (many) latches into the Row of capacitors. This dual-task ---- read, then write ---- makes writing the slower of the 2 memory activities.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.