I'm a noobee to HDL based design.
I've built a Simple Dual Port memory using the fpga's IP tools and instantiated it in a schematic.
I'm implementing a custom external cpu interface (with hand shake) with the fpga and one of the operations is to write a byte of data to the fpga memory cell defined above
I am attempting to write, in verilog, a FSM that will control operations on the "Write" side of the memory.
Question -- Memory is instantiated in a schematic along with it's associated address register/counter.
For a specific state in the FSM, I want to write data (coming from the fpga input - identified as a bus) to the memory (memory data is a bus) and increment the address counter associated with the memory.
So -- incoming data (bus), memory data in (bus), and memory address register/counter are all external to the verilog FSM and all defined in a schematic
How can I make the FSM (verilog) aware of these schematic related components and have the verilog code work with them -- especially the increment memory address counter operation.
I hope I've explained this well.
All the documents I have found on verilog/FSM/FSMD don't speak to controlling registers/busses external to the FSM code.