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I'm a noobee to HDL based design.

I've built a Simple Dual Port memory using the fpga's IP tools and instantiated it in a schematic.

I'm implementing a custom external cpu interface (with hand shake) with the fpga and one of the operations is to write a byte of data to the fpga memory cell defined above

I am attempting to write, in verilog, a FSM that will control operations on the "Write" side of the memory.

Question -- Memory is instantiated in a schematic along with it's associated address register/counter.

For a specific state in the FSM, I want to write data (coming from the fpga input - identified as a bus) to the memory (memory data is a bus) and increment the address counter associated with the memory.

So -- incoming data (bus), memory data in (bus), and memory address register/counter are all external to the verilog FSM and all defined in a schematic

How can I make the FSM (verilog) aware of these schematic related components and have the verilog code work with them -- especially the increment memory address counter operation.

I hope I've explained this well.

All the documents I have found on verilog/FSM/FSMD don't speak to controlling registers/busses external to the FSM code.

Thanks

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    \$\begingroup\$ which "fpga's IP tools" are you asking about? What tool did you use to make the schematic design (where you instatiated the memory)? What tool set are you using in general? \$\endgroup\$ – The Photon Mar 18 '17 at 15:29
  • \$\begingroup\$ This is like asking "How do I make the table of contests list only sections and not sub-sections?" without telling us which word processor you're using. \$\endgroup\$ – The Photon Mar 18 '17 at 15:36
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You don't say what FGPA or what tools you're using, so this answer can only be very generic.

You have to choose whether the "top level" of your design is going to be schematic (block diagram) or HDL (Verilog).

If schematic, then you need to instantiate your Verilog module as a block in the block diagram. The module ports in the Verilog code will correspond to "pins" on the block in the block diagram, and you'll wire those to the corresponding pins on the other IP you've already got there.

If HDL, then the block diagram containing your other IP must itself have external connections, which then become the module ports of a "black box" module that you instantiate in your Verilog top level module. Make the connections between this module and the rest of your FSM code using ordinary Verilog statements.

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  • \$\begingroup\$ I kept it general because I did not want to get into tool, top level, etc because that is not my question. Question is very specific to FSM verilog code. How do you tell a verilog module about an input/output that the code is going to manipulate when the input/output registers are instantiated external in a schematic. I'm using Xilinx, top level right now is schematic, most of my work (right now) will be schematic, but I'm attempting to define a FSM that will control various memory locations in verilog. \$\endgroup\$ – JHinkle Mar 18 '17 at 16:11
  • \$\begingroup\$ You list those inputs and outputs as ports in your module declaration. You didn't already know this? \$\endgroup\$ – Dave Tweed Mar 18 '17 at 16:18
  • \$\begingroup\$ I'm an old retired designer that is attempting to learn Verilog. I'm aware that it needs to be declared in the input of the module. Question is - I have an external counter (mem address register) that CC16CE - clk enable async clear -- do I just define the clk enable as in input wire and tell thel the HDL module anything else? Thanks \$\endgroup\$ – JHinkle Mar 18 '17 at 17:03
  • \$\begingroup\$ I've given up and have committed to learning how to do this 100% HDL. \$\endgroup\$ – JHinkle Mar 19 '17 at 17:38

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