I currently dig into the design incorporating an application processor and one piece of DDR3 memory. I already found out how the individual signal groups are formed and about the guidelines concerning trace length matching.
What I can not figure out without going quite deep : 1.)Why must the clock diffpair (and therefore the ADDR/CMD/CTRL groups) be longer than the DQ lines?
2.) Why isn't there a lower limit on the trace length of the DQ signals? and
3.)Is the ODT sertting individual for each line or does the tuning process take one value for all the data lines?
Thanks a lot!