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I currently dig into the design incorporating an application processor and one piece of DDR3 memory. I already found out how the individual signal groups are formed and about the guidelines concerning trace length matching.

What I can not figure out without going quite deep : 1.)Why must the clock diffpair (and therefore the ADDR/CMD/CTRL groups) be longer than the DQ lines?

2.) Why isn't there a lower limit on the trace length of the DQ signals? and

3.)Is the ODT sertting individual for each line or does the tuning process take one value for all the data lines?

Thanks a lot!

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The minimum length of the DQ lines does not matter because you will just change how you terminate your lines. Depending on how many sockets you have will change the termination load. You need impedance matched boards for this reason. I haven't seen the more recent development guidelines, but board layouts are pretty much given to you.

The control groups are longer due to "cross talk", and this is why you have the WR_DATA_DELAY value in the control registers. You make the control lines as long as you need to, and then you add some time for the setup.

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  • \$\begingroup\$ I don't understand your first sentence. Could you elaborate a bit more on that? For the question, assume the case that a a single memory device point-to-point topology is used. Also, what do you mean by "The control groups are longer" due to crosstalk? \$\endgroup\$ – Junius Mar 20 '17 at 16:22
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    \$\begingroup\$ @Junius Regarding the first statement: en.wikipedia.org/wiki/Characteristic_impedance Regarding the second, you generally have a delay in arrival times on the DQ lines, so you add a few pS delay by making the control lines longer. You can also add "wait" states. If you dig into the DDR3 documentation, you'll find details on all of these quirks. \$\endgroup\$ – b degnan Mar 20 '17 at 17:07
  • \$\begingroup\$ I know about the concept of characteristic impedance but impedance matching does not depend on length matching... \$\endgroup\$ – Junius Mar 20 '17 at 17:31
  • \$\begingroup\$ @Junius read up on any DDR3 IC, and you'll get an input impedance specification, you then use transmission line math to figure out the termination values. I assume there's a cookbook for this, but when I do it I have always just read all of the specifications, pushed through the math, and had success. The DDR3 specification will give you all of your answers. \$\endgroup\$ – b degnan Mar 20 '17 at 17:53
  • \$\begingroup\$ Ok, i will dig further.. The people I have talked to so far told that it is usually sufficient to try out different drive levels(=different driver output impedances) on the memory controller side and find out which one produces the best signal integrity. But of course, doing the math would be good idea anyway. Still i don't see what impedance matching has to do with length matching, since transmission line length does not influence impedance. \$\endgroup\$ – Junius Mar 20 '17 at 18:24

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