The ARM and Thumb modes are word-aligned and halfword-aligned. I understand this means that if it's in ARM mode, the start of addresses must be divisible by 32, and if it's in Thumb mode it has to be divisible by 16. But how does this relate to the PC's bit 0 never used for anything? (The instructor said that because of that they used PC's bit 0 to show whether it's in thumb or ARM mode since it wasn't being used for anything else, but before that I'm confused about the relation between alignment and PC's bit 0)
bx instruction copies bit 0 to the
T status bit, so it selects between ARM and Thumb mode on branch.
So, to jump to ARM code at address 0:
mov r0, 0 bx r0
To jump to Thumb code at address 0:
mov r0, 1 bx r0
To jump to Thumb code at address 2:
mov r0, 3 bx r0
ARM code cannot exist at address 2, because that would violate the alignment constraint. Neither ARM nor Thumb code can start at odd addresses, so the LSB of the address is always zero, and the bit is reused to select the new mode in the
To allow easy return from subroutines, bit 0 of the
lr register reflects the Thumb state from before the function call after a
blx instruction. So:
mov r0, #2f blx r0 1: b 1b .thumb 2: bx lr
will load the address of the
2 label with the bit 0 set (as the label refers to Thumb code) into
blx loads the address of the
l label with bit 0 clear (because it refers to ARM code) into
lr and jumps to the
bx lr instruction, which uses the
lr to return to the endless loop in ARM mode.
I understand this means that if it's in ARM mode, the start of addresses must be divisible by 32, and if it's in Thumb mode it has to be divisible by 16.
No; this means that in ARM mode, instructions must start at an address divisible by 4, or divisible by 2 in Thumb mode.
Numbers that are divisible by 4 are also divisible by 2.
Numbers that are divisible by 2 are even; they always have their low bit (bit 0) set to 0.