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I tried to distribute a current via pmos and nmos current mirrors (see the schematic below).

enter image description here

While the pmos and nmos mirros itself work fine, the distribution from a nmos to a pmos mirror yields an error. The undermost red curve is the current through M9 (The first pmos mirror). This works fine. The other red curve is the current through M18 and M21 (The mirrored nmos current). Here I get a differnce. The mirroring in pmos mirror M18, M19 then works fine again (blue curve).

My suggestion is that the mirroring depends on the Vds of the transistors but actually I'm not sure. Can someone explain why this isn't working properly and how to fix it?

Edit: I'm aware of the channel-length issue. Therefore I have used large transistors with a W/L ratio of 1u/8u (schematic). Vdd is set to 1.2V

enter image description here

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2 Answers 2

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Notice the tilt in this IV plot? Its for a bipolar.

FETs have the same tilt, except with FETs you have the degree-of-freedom to PICK A LONGER CHANNEL. Do so.

Examine 1u, 1.5u, 2u, 3u, 4u (scaling the Widths proportionately) and you'll be delighted. enter image description here

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  • \$\begingroup\$ I'm aware of the channel-length issue. Therefore I have used transistors with a W/L ratio of 1u/8u (please have a look in the schematic). Is there another effect one has to take into account? \$\endgroup\$
    – Max
    Mar 20, 2017 at 9:50
  • \$\begingroup\$ I see the top left Vin is 1.2 volts. Either reduce the input current, or make the FETs be (instead of W=1/L=8) W=10, L=8. Or W=100,L=8. And if these are deep-submicron devices, evaluate W=100/L=10 or W=100/L=12. If tweaking the lengths is permitted. \$\endgroup\$ Mar 20, 2017 at 16:20
  • \$\begingroup\$ The mirroring within a nmos or pmos mirror works nice. The problem is the mirroring from a nmos to a pmos mirror. In our case the wire of M18. I expect that the difference arises from the drain voltage in this wire. On the left hand side we have 123mV and on the right hand side 838mV at the drain of the nmos. What do you think about this idea? \$\endgroup\$
    – Max
    Mar 20, 2017 at 20:38
  • \$\begingroup\$ 3 choices: 1) reduce the current you are mirroring, 2) widen the FETS, 3) increase the VDD \$\endgroup\$ Mar 21, 2017 at 3:37
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Have you checked all the transistors (specially NMOS) are working in its correct operation region?

By inspecting the cadence capture you have uploaded, you can observe that Vg value of the NMOS current mirror is set to 123.7 mV, thus it is working in subthreshold region.

When configuring MOS transistors working as current mirrors, these should operate in strong inversion (and of course, in saturation given that is diode-connected)

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