The Junction-to-case (bottom) thermal resistance of the TPS7A4701 LDO regulator is 1.7 °C/W. It is explained in the TI's app note "Semiconductor and IC package thermal metrics" that this metric refers to the thermal resistance between the junction and the exposed pad of the package.

On the other hand, the Junction-to-board thermal resistance of the regulator is 11.9 °C/W. I am not sure that I understand this metric. If the junction to the bottom case (exposed pad) is only 1.7 °C/W, and the junction to board is 11.9 °C/W, so there is a 10.2 °C/W thermal resistance between the exposed pad and the board. But the exposed pad is soldered to the board, so it doesn't make sense, the thermal resistance of the solder should be very low.


The reason is they are completely different measurement procedures.

\$R_{ΘJB}\$ Has nothing to do with a heatsink. It is a JEDEC standard where \$R_{ΘJC}\$ is not.

Historically the junction-to-case thermal resistance RθJC(top) of semiconductor devices has been determined by direct measurement of the temperature difference between junction and the case surface in contact with a water cooled heatsink as described in MIL Standard 883. The results are often not reproducible because the thermocouple measurement of the case temperature is prone to error.

\$R_{ΘJB}\$ measurement is done according to JEDEC JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions — Junction-to-Board

This standard specifies the environmental conditions necessary for determining the junction-to-board thermal resistance, RθJB, and defines this term. The RθJBthermal resistance is a figure of merit for comparing the thermal performance of surface mount packages mounted on a standard board.

JEDEC standards can be downloaded with a free registration here: JEDEC Free Downloads

The standard board used in JESD51-8 is defined in JEDEC JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages


enter image description here


enter image description here

There is a JEDEC procedure, not used by TI, for measuring \$R_{ΘJC}\$ for the application purpose of attaching a heatsink to the case, JESD51-14 TRANSIENT DUAL INTERFACE TEST METHOD FOR THE MEASUREMENT OF THE THERMAL RESISTANCE JUNCTION-TO-CASE OF SEMICONDUCTOR DEVICES WITH HEAT FLOW THROUGH A SINGLE PATH.

enter image description here

enter image description here


enter image description here


\$R_{θJB}\$ is used when no heat sink is on board.

If there is a heatsink, do not use above metric and instead use \$R_{θJA}\$ which is in parallel with \$R_{θJC}+R_{θCS}+R_{θSA}~~~~\$ as the net thermal resistance.

  • \$R_{θJB}\$ Junction-to-board thermal resistance 11.9 °C/W
  • \$R_{θJA}\$ Junction-to-ambient thermal resistance 32.5 °C/W
  • \$R_{θJC}\$ (top) Junction-to-case (top) thermal resistance 27 °C/W
  • \$R_{θJC}\$ (bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W
    • \$ψ_{JT}\$ Junction-to-top characterization parameter 0.3 °C/W
    • \$ψ_{JB}\$ Junction-to-board characterization parameter 11.9 °C/W

Thus add 1.7 to your interfaces \$R_{θCS}+R_{θSA}~\$ then // with 32.5

For J= junction, C=case, S=sink, A=ambient, B=board and \$R_θ\$ means thermal resistance, although often just truncated to \$R_{JC}\$

The main revelation in the report is that the following analysis is old and obsolete, because the board does not dissipate 100% of the heat, with some cooling effect in the case to ambient.

\$R_{θJA} = R_{θJC} + R_{θCA}~\$ (obsolete)

  • \$\begingroup\$ Actually, the RθJA that is given in the datasheet is calculated without heat sink. It is calculated when the device is mounted to a PCB that is designed in accordance with the JEDEC specifications. But I still don't understand the Junction-to-board thermal resistance RθJB. \$\endgroup\$ – Vadim Mar 20 '17 at 17:38
  • \$\begingroup\$ @Vadim From how I read it, RθBA is heat resistance through the lid not the bottom. RθJB is a combination of RθBA and resistance through the bottom to a standard pad and board thickness to air. That is... RθBA is the total resistance to ambient through both the top and the bottom / board. See figure 6 of the metrics document. \$\endgroup\$ – Trevor_G Mar 20 '17 at 17:42
  • 1
    \$\begingroup\$ Yes top + bot thermal resistance of case without heat sink computes board temp rise using \$R_{θJB}\$ sometimes called solder point to junction thermal resistance. Note location of thermocouple used for verification. \$\endgroup\$ – Sunnyskyguy EE75 Mar 20 '17 at 17:55
  • \$\begingroup\$ Agreed @TonyStewart.EEsince'75, and the numbers quoted seem to make sense for that. aside.. 75 eh... four years more than me :) \$\endgroup\$ – Trevor_G Mar 20 '17 at 18:08

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.