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If we assume that allowable inputs a, b and c are applied to the following logic gates, what is the output in terms of a,b and c?

enter image description here

I ran into the above problem, but I'm not sure if it makes sense. Because some NOT logic gates have two inputs which is not what I expect. I wonder if the problem is wrong or I'm missing something.


I need to calculate the output of the logic gates in terms of a, b and c with logic operators like: \$\bullet \$ for AND, \$+\$ for OR, \$\overline{a}\$ for NOT \$a\$

I appreciate if anybody can help.

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    \$\begingroup\$ You're missing the session of your course that explained what those gates are. \$\endgroup\$ – Ignacio Vazquez-Abrams Mar 20 '17 at 17:35
  • \$\begingroup\$ The additional input controls whether the output is connected to H or L at all. That undefined state is called Hi-Z and it's required for bus systems where multiple outputs are connected to one bus line. \$\endgroup\$ – Janka Mar 20 '17 at 18:32
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    \$\begingroup\$ Your mysterious gate is a tri-state inverting buffer. Here is an example of such chip: assets.nexperia.com/documents/data-sheet/74HC_HCT125.pdf (although this one has the ENABLE input inverted relative to yours, and does not invert the output) \$\endgroup\$ – peufeu Mar 20 '17 at 18:43
  • \$\begingroup\$ @peufeu I'm going to study the document. \$\endgroup\$ – user4838962 Mar 20 '17 at 18:44
  • \$\begingroup\$ I can't find the part# which corresponds to your "inverter", here is a closer one: inverting output (like yours), and active-low OUTPUT_ENABLE (OE) signal (unlike yours): ti.com/lit/ds/symlink/sn74lvc1g240.pdf \$\endgroup\$ – peufeu Mar 20 '17 at 18:51
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As a theoretical logic diagram this is pure nonsense. Inverter has only one input and connecting 2 outputs together means nothing.

As practical circuit diagram this can be valid. the special 2 input inverters can really be disconnect-able by the disabling signals. In practice we say "they have 3-state outputs". The 3rd state is called "high-Z" and that means "disconnected by internal electronic switch."

The rightmost a and c should not be the same as the leftmost a and c.

But if you really have this as written and 0 means "disabled" for the special inverters, then you have the following truth table:

a b c .....out

0 0 0 .....undefined (=no proper input to the rightmost inverter)

0 0 1......0

0 1 0 .....undefined

0 1 1 .....0

1 0 0......0

1 0 1 .....smoke (=a short circuit)

1 1 0.....0

1 1 1 ....1

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  • \$\begingroup\$ Thanks, if we assume we have special 2-input inverters, I wonder if it is possible to calculate the output in terms of a, b and c and the logic operations between them. \$\endgroup\$ – user4838962 Mar 20 '17 at 18:26
  • \$\begingroup\$ @user4838962 no boolean equation is equivalent with this truth table, because boolean equations have only variables that can be 0 or 1. In addition the operators Joint and DisableInv are missing. But nothing prevents you to expand the Boolean algebra to have additional states Hi-Z, Undefined and Smoke and a new operators Joint and DisableInv \$\endgroup\$ – user287001 Mar 20 '17 at 18:50
  • \$\begingroup\$ Thanks, I wonder if joint operator is the same as OR operator. I feel like because a joint is where two wires merge, if any of the wires is on, the joint output is on. Therefore joint is acting like OR gate. I'm not sure. \$\endgroup\$ – user4838962 Mar 20 '17 at 19:04
  • \$\begingroup\$ @user4838962 Joint = OR if the outputs cannot actively pull down, only connect to + voltage. This is very rare, It has name "uncommitted emitter output type" More common is so called "open collector type output" that only pulls down to Ground. For them Joint = AND. For TTL outputs the Joint is forbidden because 0 Joint 1 = 1 Joint 0 = Smoke. \$\endgroup\$ – user287001 Mar 20 '17 at 19:11

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