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I am confused about what happens when we use a Bimodal branch predictor in the MIPS architecture shown in the image below.

I am considering the case where there is already a branch delay slot implemented and it uses a 1024 entries BTB and a branch predictor with a 2-bit saturating counter which gives the direction as taken or not taken.

My thinking is as follows:

Case 1 - Conditional branch is fetched.Checks for an entry in BTB. If there is an entry, then,a target address is predicted from BTB and the branch direction is taken, but at the execute stage we compare the predicted target address with the actual target address, if they don't match then at the fetch stage we kill the fetched instruction and, then we get the correct target address as follows at the fetch stage:

if(misprediction) PC value = correct target address

Case 2 - Conditional branch is fetched.There is no entry in BTB. So the branch is resolved only at the execute stage.

Case 3 - Unconditional branch is fetched. Branch direction is always taken and an entry is found in BTB, then the target address is predicted from the BTB. And at the execute stage we compare the predicted target address with the actual target address, if they don't match then at the fetch stage we kill the fetched instruction and, then we get the correct target address as follows at the fetch stage:

if(misprediction) PC value = correct target address

Is this correct?

enter image description here

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    \$\begingroup\$ How on earth can you mispredict an unconditional branch? So, why pollute the BTB with it? \$\endgroup\$ – Brian Drummond Mar 20 '17 at 23:30
  • \$\begingroup\$ @BrianDrummond:So there is no need to make an entry of unconditional branches? I am kind of confused.Could you please explain what should be entered into BTB and what to do when there is a branch misprediction? \$\endgroup\$ – pavikirthi Mar 20 '17 at 23:34

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