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I would like to ask some help to better understand limitations of multi-project wafer services (MPW).

In nutshell, i found about the service, that it merges many projects on wafer, so one project only have to pay for a share of its surface. While it is easy to understand, that i pay only for 100 mm2 of an area of 70000 mm2 so it costs less, i nowhere found to mention, that asic projects may have different amount of layers for their design. Number of layers could be anywhere from 6 to 35 and even more. If i need for example 30 layers for my design, and there are only projects with demand of 15..20 layers, how an MPW service can merge my project with cost effectivity? Can it do that at all?

I dont know, if my question involves any industrial secret or not, tell me if i was that careless.

I will be happy with any reference to internet blogs, e-docs, books or anything about the question.

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  • \$\begingroup\$ Generally you are not free to specify all such parameters, you have a limited set of processes to chose from. \$\endgroup\$ – PlasmaHH Mar 21 '17 at 15:02
  • \$\begingroup\$ Definitely not cost effective.. but doable. \$\endgroup\$ – 12Lappie Mar 21 '17 at 15:05
  • \$\begingroup\$ 35 layers is a heck of a lot and probably only applicable to high-end Intel designs. Note that every additional layer is a potential source of yield problems. \$\endgroup\$ – pjc50 Mar 21 '17 at 15:21
  • \$\begingroup\$ @pjc50 Actually I would expect the smallest Intel processes to have less layers as these are CMOS only. I would expect these to use about 25 masks or so (just a guess, I don't work with these). Actually 35 layers is quite normal for more complex processes like with SiGe Bipolars+CMOS with special (RF) options. \$\endgroup\$ – Bimpelrekkie Mar 21 '17 at 15:34
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I highly doubt you're making something more complicated than the Alpha 21064 CPU, and so I highly doubt you really need more than the 3 metal interconnect layers that was used by that CPU.

It sounds like you think that every chip designer arbitrarily uses however many layers they feel like using this week, and then later the fab does whatever it takes to make that happen.

In theory, yes -- a fab could theoretically accept a chip design that requires 9 metal interconnect layers plus a few chip designs that requires fewer layers, and the fab could more-or-less automatically insert vias and metal to pass signals through the "skipped" layers of the simpler chips up to the top bonding pad layer, and fabricate all those designs on the same wafer.

In practice, what happens is that the chip designer (like a PCB designer) asks the fab what their capabilities and for the design rules for that process. Typically a fab has a few different processes, each one with its own dedicated production line. One process is least expensive and simple with few layers and large, slow transistors. Another process is most expensive with more layers (but still far fewer layers than AMD's fab) and smaller linewidths that can be used to fabricate faster transistors. Often there is no one "best" process -- there's one high-speed process that can't handle high voltages; there's a separate high-voltage process that's really slow; etc.

The production line has already been set up with a certain number of layers of a specific kind. If you want more or different layers, you have to go to a different production line. If a chip needs to be high-speed and high-voltage and high-density, even if each one is within the capabilities of one or another of the fab's production lines, we still risk not being able to fab your chip at all because none of the available lines can handle that specific combination.

The chip designer (like a PCB designer) picks a process before even starting to lay out the chip and tries very hard to keep the design within the capabilities and design rules of that process.

If the chip designer finds the chip doesn't really need all the capabilities of that process, then the chip designer manually adds vias and metal to pass signals through the "skipped" layers. (And meanwhile seriously considers switching to a lower-cost process).

It would be nice if you could simply download that capability information from the fab's website. But in practice the chip designer needs to sign a confidentiality agreement (CDA) and work with some university professor who already knows how to shepherd student chip designers through the process.

So, for example, Europractice requires signing a non-disclosure agreement (NDA), filling out an application and fax it back (!), etc., etc.

So, for example, the I3T80 Process available through MOSIS page describes how to get the capabilities and design rules for that process -- get an account with MOSIS; sign a confidentiality agreement, etc., etc. That process is one of the standard foundry processes at On Semicondustor who publishes the I3T80: 0.35 um Process Technology datasheet.

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  • \$\begingroup\$ Design will have dynamic ram matrix, heat sensor, io interface, registers and state machines. Supposed to be mature technology. Its only new by the target market. I found on a Samsung blog about their statistics from the past, memory device around 256 megabit would have 25-30 layers. I dont know if i totally missed something about. \$\endgroup\$ – cocox Mar 21 '17 at 20:09
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    \$\begingroup\$ I found no smaller node size at OnSemi than 350 nm. I think i should go for 130 nm, or even less. On 130 nm, 256 megabits of 8 ff memory cells, and components around, die size could go up to 100 mm2. And no, ofc its not my intention to fight all that way in low level development, i should ask a design house to help, i know. All my concern ends at logical level of the design, Europractice-IC named it as "front-end design" on page 4 here: ( europractice-ic.com/docs/Annual_report_2011.pdf ). \$\endgroup\$ – cocox Mar 21 '17 at 22:03
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If i need for example 30 layers for my design, and there are only projects with demand of 15..20 layers

It does not work exactly like that.

You talk about layers but what you mean is masks. Not every layer in your design directly relates to a mask. Some AND/OR/NOR... functions are used to translate the (design) layers into physical masks.

For a given IC manufacturing process a certain minimum number of masks is needed. You're not "free" to select which layers/masks you want to use as the IC manufacturing process is required to follow a certain fixed "recipe" to make the ICs. Only some deviations are allowed, meaning some masks are optional, for example a mask for a high-resistance poly-resistor or a mask which defines an extra metal layer.

On a Multi-project-wafer all masks needed by all projects must be present. If there are 10 different designs and only one needs the high-res poly mask then it will actually be available for all those projects. The masks are shared for the MPW so you have no choice.

You do have the choice to use the mask option or not. If you don't use the high-res poly resistor in your design you are free to do so. This also means that if your design goes into mass production you do not need that high-res poly mask. So then you will not be paying for it.

If none of the designs on the MPW use the optional mask then in principle it could be skipped for the MPW as well.

Documents about this are generally not available to anyone unless you're an employee or customer at some Foundry. My answer is based on my personal experience as an IC designer and dealing with these foundries.

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  • \$\begingroup\$ And sometimes even as a MPW customer you need to go through an accreditation process to get these informations... :/ \$\endgroup\$ – PlasmaHH Mar 21 '17 at 15:23
  • \$\begingroup\$ @PlasmaHH But of course, they need to know that you're serious and not a competitor's spy looking for information. Having a large company behind you / your company helps tremendously. Big Foundries like TSMC don't even want to talk to you directly unless you're big enough for them. \$\endgroup\$ – Bimpelrekkie Mar 21 '17 at 15:30
  • \$\begingroup\$ @FakeMoustache thank you for details. I am thinking about an asic design. I found out nre cost is hard problem on start. Found companies for MPW and MLM runs, and blogs about they are helpful to the budget in start. (Well, i not found exact numbers how much nre cost % they can save for first prototypes to get into my hand.) Wanna be sure, i dont do mistake if i count on those starting cost advantages for sure - MPW in this case. That is the only point for my question. I would apologise that i am a newbie on that domain, and i was not able to address correct terms. \$\endgroup\$ – cocox Mar 21 '17 at 17:51
  • \$\begingroup\$ I am thinking about an asic design Good luck with that, I hope you realize that you would be entering a very specialist area. Ideally you'd hire a company with relevant experience to do the design for you. If you have no experience with ASIC design and everything related to that, then do educate yourself. Also you do need a good reason to make an ASIC so that you can warrant the NRE cost which can be very high. I work/worked on specialist RF ASICs, NRE budgets of around 1 million Euros are no exception ! Its not only the MPW cost but design, testing etc. \$\endgroup\$ – Bimpelrekkie Mar 21 '17 at 18:41
  • \$\begingroup\$ @FakeMoustache If you are interested to be cofounder in a likely looser project (i cannot promise any success for sure), i will be happy. Funding is still a problem, and anything can help to business logistic, worth to look for, that is why i started this topic in the middle of nowhere. I know, it could seem strange, but this is how it always seems when someone try to push forward the world into its future, and world fights back with everything it have. That is a free choice to everyone, which side to fight for. \$\endgroup\$ – cocox Mar 21 '17 at 19:57

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