Other answers well explain the bit level sampling, yet I wanted to explain deeper the sub-bit activities and details about clock skew and phase.
how asynchronous works.
The sender and retriever agree on format: a frame of 1 start-bit, N data bits, optional parity and 1, 1.5 or 2 stop bits.
They agree on an approximate common communication rate like 1/115,200 seconds per "bit" or baud. Each side runs its own clock. The result is that the clocks may be slightly different from each other. Segal's law. In theory, about 10% difference is allowed, in practice, it is more like 5%.
Yet an important element the do not share is phase of the their clocks. Even if both sender and receiver had identical clock frequencies the phase relationship between the sender/receiver clocks is not controlled. With nearly identical clocks, this phase slowly shifts.
To cope with this phase difference, the receiver samples at a higher rate than the baud. Let us assume 16x faster.
A receiver wakes up to look at its input, which it is sampling at 16x baud. If input is not idle, it waits until the line is idle for a while.
Once the input is in the idle state (no data being sent), the receiver looks for a sample transition to the active state. Once this is detected, a good receiver also looks 1/2 bit time (8x samples) later for a continuing active state. If this is detected then a state bit is found and the phase (within 1/16 of a bit) is detected of incoming data. If not, the spurious signal is usually quietly ignored and the receiver rejects this as noise and begins again as above.
The next N samples, done at full bit width from the start bit 1/2 bit offset, assumes the line is data and the LSbit to MSbit is read.
Sometimes a parity bit is included.
Lastly the next 1 (or rarely 2) bits are sampled (in their middle) and should be in the idle state. If not, the frame received is said to have a stop bit error or frame error. A long start bit is a special framing error called a break.
After the last stop bit is sampled, near its middle, the receiver is immediately ready for another start bit. This allows the sender and receiver's clocks to be up to about 5-10% off from each other and communication succeeds.
How does the receiving device "know" that I'm sending a start bit followed by 6 0s?
In OP's case, sending x03 or b0000-0011, after the line has been idle (1-1-1-1-... state) for a while and the receiver is ready, the sender outputs a start 0, 1-1-0-0-0-0-0-0, stop bit 1. The receiver detects the start bit, data and stop bit. Success!
Additional attributes, not covered, include over-sampling of data with a majority detect, break, parity details, higher level protocols, auto-baud detection, etc.