I read somewhere that bad VHDL code can lead to FPGA damage.
Is it even possible to damage a FPGA with VHDL code? What kind of conditions would cause this and what are the worst case scenarios?
Adding to @Anonymous's answer, there are designs you can build which can damage the fabric of an FPGA.
For starters if you build a very large design consisting of huge quantities of registers (e.g. 70% of the FPGA) all clocked at nearing the FPGAs maximum frequency, it is possible to heat the silicon considerably. Without sufficient cooling this can cause physical damage. We lost a $13k FPGA because it overheated due to the dev-kit having a terrible cooling system.
Another simpler case can be combinational loops. For example if you instantiate three not gates chained together in a ring, and disable or ignore the synthesizers warnings about such a structure, you can form something which is very bad for an FPGA. In this example you'd make a multi-GHz oscillator which could produce a lot of heat in a very small area, probably damaging the ALM and surrounding logic.
Code is not a right word in this context. While Verilog or VHDL look like program, the output of the compiler is a configuration which is loaded into the FPGA chip forming electronic circuit within it.
Two types come to my mind:
Misconfiguring a block of input pins as outputs might do it if whatever else is driving them is stiff enough.
I don't know if configuring some pins for LVDS or one of the LVCMOS standards while the IO bank is powered from an overly high voltage (3.3V power with a 1.8V IO standard for example, or the opposite on an input) would do it?
Obviously thermal problems may be a possibility by doing something silly like instantiating many, many, ring oscillators.
FPGAs can be reconfigured at runtime with a new (partial) bitstream. Normally, this stream is loaded from an external source, but you can also create it by your self in the FPGA (e.g. by an embedded softcore CPU). Using such a solution for e.g. dynamically relocating subdesigns, doesn't provide all the consistency checks as done by the vendor tools. So if your algorithm is broken, you might enable the false path transistors in an FPGA and burn them.
You could also chose false operations modes for FPGA primitives like PLLs or transceivers.
Dynamic reconfiguration is like self modifying code in software.