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I am using Spartan 3E Starter Kit and I need to store a sequence of bits around 1MB long. It is a constant bitstream and will be known to me at the time of programming the board. I need to be able to read out one bit at a time from this stream. I believe I need to put this sequence of bits in the flash memory on the board since I need it to be persistent even when power is not given to the board. Any clue how that is to be done?

Can someone point me to a tutorial on how to put this data on the flash and how to read it out to some other module that processes it?

Xilinx Devices:

  • Spartan-3E FPGA (XC3S500E-4FG320C)
  • CoolRunner™-II CPLD (XC2C64A-5VQ44C)
  • Platform Flash (XCF04S-VO20C)
  • Clocks: 50 MHz crystal clock oscillator

Memory:

  • 128 Mbit Parallel Flash (28F256)
  • 16 Mbit SPI Flash (M25P16)
  • 64 MByte DDR SDRAM (MT46V16M16)
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  • \$\begingroup\$ It is 1MB (Megabyte). But I dont think that will affect us much as memories are much larger then 1MB. \$\endgroup\$ – Neel Mehta Apr 7 '12 at 9:27
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    \$\begingroup\$ The best tutorial is probably reading the datasheet for the part. Pick either the parallel or the SPI, then plan out the state machines you need for the interface. \$\endgroup\$ – mng Apr 8 '12 at 21:11
  • \$\begingroup\$ The basic documentation doesn't mention any way to store data in the flash memory (available on the FPGA) and interfacing with them. I have heard that using Xilinx-EDK, I can configure something similar to a microcontroller, and use it to interface with the the memory. But I am not sure of how to proceed or how it actually works. \$\endgroup\$ – Neel Mehta Apr 9 '12 at 6:43
  • \$\begingroup\$ Is the data constant for all time, or do you need to program different boards with different data? Meaning, could you code the data directly into your HDL code? \$\endgroup\$ – The Photon Apr 14 '12 at 16:54
  • \$\begingroup\$ Xilinx has LOTS of documentation on how to store your FPGA program in flash. \$\endgroup\$ – user3624 Apr 14 '12 at 17:09
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Method 1: Create ROMs in your FPGA design

Because you have the same data in every board, one option is to use block RAMs in the FPGA, configured as ROM. To do this you instantiate a block RAM, but don't connect to the write pins. Use a synthesis directive in your HDL code or UCF file to specify the initial contents of the RAM. Read the Spartan-3 Generation User's Guide (Chapter 4) to see how to instantiate the RAM and how to access the data from the RAM. If you use Xilinx ISE, there is probably also a "wizard" to generate the RAM block and set up the initial contents for you.

Unfortunately, the Spartan-3E you are using has only 350 kbits of block RAM, not 8 Mbits like you require. For this to work then, you'll have to work out a scheme to compress your data to fit in 350 kbits. The details of how to do this depend on what kind of data you have. If your data is especially random, it might not be reasonable to get this much compression.

Method 2: Store data in external memory

You say you have a 128 Mbit parallel flash and a 16 Mbit SPI flash. You will need to read the datasheets for these parts and understand how they work. Then write a state machine into your FPGA that can access these devices. But this is your job as the FPGA designer. Some random strangers on the internet are not going to design your FPGA for you.

To store the data onto the flash initially you have two choices. First would be, if you are building these boards in volume, you can have your board assembly shop pre-program the flash devices before assembling them onto the boards. Typically you give them a data file in some format they request, and they charge you some small extra fee to have the data flashed in before assembly.

Second option: Read the datasheet for the flash device. Write an FPGA design that allows you to send data from some other interface available on your board (Ethernet, USB, SPI, I2C, whatever), and load it into the flash. At manufacturing time, you load this design temporarily into your FPGA and program your flash; then you store a different "run-time" FPGA design into the on-board configuration PROM, that doesn't have the ability to modify the FLASH, and your users won't have the ability to mess up the data.

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Do you have a soft-processor like microblaze? You can write to the DDR by specifying the base address and then writing from that address onwards. I believe you could do the same with the flash, though you'll need to check the docs for exact syntax.

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  • \$\begingroup\$ I believe Xilinx EDK (Embedded Development Kit) allows me to do what you are saying. But how do I link it with my FPGA code (verilog code) that I would use to process data after reading it from the flash? \$\endgroup\$ – Neel Mehta Apr 15 '12 at 18:16
  • \$\begingroup\$ When I did something similar, I had a microblaze that was connected to a co-processor (written in VHDL/verilog) and the data is read by the microblaze which them transfers it through Fast simplex link (FSL) to the co-processor which then does necessary processing in hardware and returns via FSL. \$\endgroup\$ – Shungun Apr 16 '12 at 15:27

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